
MAX8709
High-Efficiency CCFL Backlight
Controller with SMBus Interface
_______________________________________________________________________________________ 3
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1. V
BATT
= 12V, V
LOT
= V
REF
, V
CC
= V
DD,
V
SUS
= 5.3V, T
A
= 0°C to +85°C. Typical values are at T
A
= +25°C,
unless otherwise noted.)
LOT Input Voltage Range 0.5
V
REF
V
LOT Input Bias Current -2 +2 µA
IFB Input Voltage Range
-1.7 +1.7
380 400 420
mV
IFB Input Bias Current V
IFB
= 0.4V -2 +2 µA
IFB Lamp-Out Threshold LOT = REF
500 600 700
mV
IFB to CCI Transconductance 1V < V
CCI
< 2.5V
100
µS
CCI Output Impedance 20 MΩ
ISEC Input Voltage Range -2 +2 V
ISEC Regulation Threshold
1.20 1.25 1.30
V
ISEC Input Bias Current V
ISEC
= 1.25V -2 +2 µA
VFB Input Voltage Range -2 +2 V
VFB Input Bias Current V
VFB
= 0.5V
-0.5 +0.5
490 510 530
mV
VFB to CCV Transconductance 1V < V
CCV
< 2.7V 40 µS
VFB Zero-Voltage Crossing Threshold -10
+10
mV
CCV Output Impedance 20 MΩ
Digital PWM Chopping Frequency
200 210 220
Hz
Lamp-Out Detection Timeout Timer V
IFB
< 0.1V (Note 1)
1.14 1.22 1.30
s
SDA, SCL, SUS Input Low Voltage 0.8 V
SDA, SCL, SUS Input High Voltage 2.1 V
SDA, SCL, SUS Input Hysteresis
300
mV
SDA, SCL, SUS Input Bias Current -1 +1 µA
SDA Output Low Sink Current V
SDA
= 0.4V 4 mA
SCL Serial Clock High Period T
HIGH
4µs
SCL Serial Clock Low Period T
LOW
4.7 µs
Start-Condition Setup Time t
SU:STA
4.7 µs
Start-Condition Hold Time t
HD:STA
4µs
SDA Valid to SCL Rising-Edge Setup Time,
Slave Clocking-In Data
t
SU:DAT
250
ns
SCL Falling Edge to SDA Transition t
HD:DAT
0ns
SCL Falling Edge to SDA Valid,
Reading Out Data
T
DV
700
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