MAX6870/MAX6871
EEPROM-Programmable Hex/Quad
Power-Supply Sequencers/Supervisors with ADC
______________________________________________________________________________________ 43
Configuring the Watchdog Timers
(Registers 3Ch–3Fh)
A watchdog timer monitors microprocessor (µP) soft-
ware execution for a stalled condition and resets the µP
if it stalls. The output of a watchdog timer (one of the
programmable outputs) connects to the reset input or a
nonmaskable interrupt of the µP.
Registers 3Ch–3Fh configure the watchdog functionality
of the MAX6870/MAX6871. Program each watchdog
timer to assert one or more programmable outputs (see
Tables 10–21). Program each watchdog timer to reset on
one of the GPI_ inputs, one of the programmable out-
puts, or a combination of one GPI_ input and one pro-
grammable output.
Each watchdog timer features independent initial and
normal watchdog timeout periods. The initial watchdog
timeout period applies immediately after power-up, after a
reset event takes place, or after enabling the watchdog
timer. The initial watchdog timeout period allows the µP to
perform its initialization process. If no pulse occurs during
the initial watchdog timeout period, the µP is taking too
long to initialize, indicating a potential problem.
The normal watchdog timeout period applies in every
other cycle after the initial watchdog timeout period
occurs. The normal watchdog timeout period monitors
a pulsed output of the µP that indicates when normal
processor behavior occurs. If no pulse occurs during
the normal watchdog timeout period, this indicates that
the processor has stopped operating or is stuck in an
infinite execution loop.
Disable or enable each initial timeout period through reg-
isters 3Ch and 3Eh. Registers 3Dh and 3Fh program the
initial and normal watchdog timeout periods, and enable
or disable each watchdog timer. See Tables 27 and 28
for a summary of the watchdog behavior.
Fault Detector
Registers 60h–62h store all fault conditions, including
undervoltage, overvoltage, GPI_, and watchdog timer
faults (see Table 29). Fault registers are read-only and
lose contents upon power removal. The first read com-
mand from the fault registers after power-up gives invalid
data. Any MR assertion writes to the fault register.
Reading the fault register clears all fault flags. Both GPI_
Table 27. Watchdog Inputs (Addresses
3Ch (Watchdog 1), 3Eh (Watchdog 2))
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