
MAX6660
Remote-Junction Temperature-Controlled
Fan-Speed Regulator with SMBus Interface
_______________________________________________________________________________________ 3
Note 1: Junction Temperature = T
A
. This implies zero dissipation in pass transistor (no load, or fan turned off).
Note 2: T
RJ
, Remote Temperature accuracy is guaranteed by design, not production tested.
Note 3: Guaranteed by design. Not production tested.
Note 4: The MAX6660 includes an SMBus timeout, which resets the interface whenever SMBCLK or SMBDATA has been low for
greater than 25ms. This feature can be disabled by setting bit 2 of the Fan Gain register at 16h/1Bh to a 1. When the timeout
is disabled, the minimum clock frequency is DC.
Note 5: Note that a transition must internally provide at least a hold time in order to bridge the undefined region (300ns max) of
SMBCLK’s falling edge.
ELECTRICAL CHARACTERISTICS (continued)
(V
CC
= +3V to +5.5V, V
VFAN
= +12V, T
A
= -40°C to +125°C, unless otherwise specified. Typical values are at V
CC
= +3.3V and
T
A
= +25°C.) (Note 1)
PARAMETER SYM BOL CONDITIONS MIN TYP MAX UNITS
Tach Input Transition Level V
VFAN
= 12V 10.5 V
Tach Input Hysteresis V
FAN
= 12V 190 mV
Current-Sense Tach Threshold 20 mA
Current-Sense Tach Hysteresis 0.3 mA
Fan Output Current 250 mA
Fan Output Current Limit (Note 3) 320 410 mA
Fan Output On-Resistance R
ONF
250mA load 4 Ω
SMBus INTERFACE: SMBDATA, ALERT, STBY, OVERT
Logic Input Low Voltage V
IL
V
CC
= +3.0V to +5.5V 0.8 V
V
CC
= +3.0V 2.2
Logic Input High Voltage V
IH
V
CC
= +5.5V 2.6
V
Input Leakage Current I_leak V
IN
= GND or V
CC
-2 +2 µA
Output Low Sink Current I
OL
V
OL
= 0.4V 6 mA
Input Capacitance C
in
5pF
Output High Leakage Current V
OH
= 5.5V 1 µA
Serial Clock Frequency f
SCL
(Note 4) 0 100 kHz
Bus Free Time Between Stop
and Start Conditions
t
BUF
4.7 µs
Start Condition Setup Time 4.7 µs
Repeat Start Condition Setup
Time
t
SU:STA
90% to 90% 50 µs
Start Condition Hold Time t
HD:STA
10% of SMBDATA to 90% of SMBCLK 4 µs
Stop Condition Setup Time t
SU:STO
90% of SMBCLK to 10% of SMBDATA 4 µs
Clock Low Time t
LOW
10% to 10% 4.7 µs
Clock High Time t
HIGH
90% to 90% 4 µs
Data Setup Time t
SU:DAT
90% of SMBDATA to 10% of SMBCLK 250 ns
Data Hold Time t
HD:DAT
(Note 5) 0 µs
Receive SMBCLK/SMBDATA
Rise Time
t
R
1µs
Receive SMBCLK/SMBDATA
Fall Time
t
F
300 ns
SMBus Timeout t
TIMEOUT
SMBDATA and SMBCLK time low for reset
of serial interface
25 40 ms
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