Rainbow-electronics MAX5531 Manual do Utilizador descarregar pdf (Página 5)

MAX5530/MAX5531

Ultra-Low-Power, 12-Bit,

Voltage-Output DACs

_______________________________________________________________________________________ 5

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

TIMING CHARACTERISTICS (V

= 4.5V TO 5.5V)

Serial Clock Frequency f

SCLK

16.7

MHz

DIN to SCLK Rise Setup Time t

15 ns

DIN to SCLK Rise Hold Time t

0ns

SCLK Pulse-Width High t

24 ns

SCLK Pulse-Width Low t

24 ns

CS Pulse-Width High t

CSW

100 ns

SCLK Rise to CS Rise Hold Time

CSH

0ns

CS Fall to SCLK Rise Setup Time

CSS

20 ns

SCLK Fall to CS Fall Setup t

CSO

0ns

CS Rise to SCK Rise Hold Time t

CS1

20 ns

TIMING CHARACTERISTICS

= +4.5V to +5.5V, T

= T

MIN

to T

MAX

, unless otherwise noted. Typical values are at T

= +25°C.)

TIMING CHARACTERISTICS

= +1.8V to +5.5V, T

= T

MIN

to T

MAX

, unless otherwise noted. Typical values are at T

= +25°C.)

Note 1: Linearity is tested within codes 96 to 4080.

Note 2: Offset is tested at code 96.

Note 3: Gain is tested at code 4095. FB is connected to OUT.

Note 4: Guaranteed by design. Not production tested.

Note 5: V

must be a minimum of 1.8V.

Note 6: Outputs can be shorted to V

or GND indefinitely, provided that the package power dissipation is not exceeded.

Note 7: Optimal noise performance is at 2nF load capacitance.

Note 8: Thermal hysteresis is defined as the change in the initial +25°C output voltage after cycling the device from T

MAX

to T

MIN

Note 9: All digital inputs at V

or GND.

Note 10: Load = 10kΩ in parallel with 100pF, V

= 5V, V

REF

= 4.096V (MAX5530) or V

REF

= 3.9V (MAX5531).

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

TIMING CHARACTERISTICS (V

= 1.8V TO 5.5V)

Serial Clock Frequency f

SCLK

010

MHz

DIN to SCLK Rise Setup Time t

24 ns

DIN to SCLK Rise Hold Time t

0 ns

SCLK Pulse-Width High t

40 ns

SCLK Pulse-Width Low t

40 ns

CS Pulse-Width High t

CSW

150

SCLK Rise to CS Rise Hold Time

CSH

0 ns

CS Fall to SCLK Rise Setup Time

CSS

30 ns

SCLK Fall to CS Fall Setup t

CSO

0 ns

CS Rise to SCK Rise Hold Time t

CS1

30 ns

1 2 3 4 5 6 7 8 9 10 ... 18 19

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