Rainbow-electronics T89C51AC2 Manual do Utilizador

Rev. B – 19-Dec-0111. Features• 80C51 core architecture:– 256 bytes of on-chip RAM– 1 Kbytes of on-chip ERAM– 32 Kbytes of on-chip Flash memoryData Re

10T89C51AC2Rev. B – 19-Dec-015. SFR Mapping The Special Function Registers (SFRs) of the T89C51AC2 fall into the followingcategories:Table 3. C51CoreS

100T89C51AC2Rev. B – 19-Dec-0118.4.4 External Data MemoryCharacteristicsTable 62. Symbol DescriptionTable 63. AC Parameters for a Variable Clock (F=40

101T89C51AC2Rev. B – 19-Dec-01Table 64. AC Parameters for a Variable Clock18.4.5 External Data MemoryWrite CycleSymbol TypeStandardClock X2 Clock X pa

102T89C51AC2Rev. B – 19-Dec-0118.4.6 External Data MemoryRead Cycle18.4.7 Serial Port Timing -Shift Register ModeTable 65. Symbol Description (F= 40 M

103T89C51AC2Rev. B – 19-Dec-0118.4.8 Shift Register TimingWaveforms18.4.9 External Clock DriveCharacteristics (XTAL1)Table 68. AC Parameters18.4.10 Ex

104T89C51AC2Rev. B – 19-Dec-0118.4.12 Float WaveformsFor timing purposes as port pin is no longer floating when a 100 mV change from loadvoltage occur

105T89C51AC2Rev. B – 19-Dec-01This diagram indicates when signals are clocked internally. The time it takes the signalsto propagate to the pins, howev

106T89C51AC2Rev. B – 19-Dec-0118.5.14 Flash Memory Table 69. Timing Symbol DefinitionsTable 70. Memory AC TimingVDD= 5 V +/- 10% , TA= -40 to +85°CFig

107T89C51AC2Rev. B – 19-Dec-0119. Ordering InformationTable 71. Possible order entriesPart Number Memory Size Supply VoltageTemperatureRange Max Frequ

iT89C51AC2Rev. B – 19-Dec-01Table of Contents1. Features ...

iiT89C51AC2Rev. B – 19-Dec-0114.1 WatchDog Programming ... 6614.2 WatchDog Timer

11T89C51AC2Rev. B – 19-Dec-01Table 6. Serial I/O Port SFRsTable 7. PCA SFRsT2CON C8hTimer/Counter 2controlTF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2# CP/RL2#T2

© Atmel Corporation 2001.Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standa

12T89C51AC2Rev. B – 19-Dec-01Table 8. Interrupt SFRsTable 9. ADC SFRsCCAP0HCCAP1HCCAP2HCCAP3HCCAP4HFAhFBhFChFDhFEhPCA CompareCapture Module 0 HPCA Com

13T89C51AC2Rev. B – 19-Dec-01Table 10. Other SFRsMnemonicAddName 76543210PCON 87h Power Control SMOD1 SMOD0 - POF GF1 GF0 PD IDLAUXR 8Eh Auxiliary Reg

14T89C51AC2Rev. B – 19-Dec-01Table 11. SFR’s mappingReservedNotes: 1. These registers are bit-addressable.Sixteen addresses in the SFR space are both

15T89C51AC2Rev. B – 19-Dec-016. Clock The T89C51AC2 core needs only 6 clock periods per machine cycle. This feature,called”X2”, provides the following

16T89C51AC2Rev. B – 19-Dec-01Figure 5. Clock CPU Generation DiagramXTAL1XTAL2PDPCON.1CPU Core10÷ 2PERIPHCLOCKClockPeripheral Clock SymbolCPUCLOCKCPU C

17T89C51AC2Rev. B – 19-Dec-01Figure 6. Mode Switching WaveformsNote: In order to prevent any incorrect operation while operating in the X2 mode, users

18T89C51AC2Rev. B – 19-Dec-01Notes: 1. This control bit is validated when the CPU clock bit X2 is set; when X2 is low, this bithas no effect.Reset Val

19T89C51AC2Rev. B – 19-Dec-017. Data Memory The T89C51AC2 provides data memory access in two different spaces:1. The internal space mapped in three se

2T89C51AC2Rev. B – 19-Dec-01The added features of the T89C51AC2 make it more powerful for applications that needA/D conversion, pulse width modulation

20T89C51AC2Rev. B – 19-Dec-017.1 Internal Space7.1.1 Lower 128 Bytes RAM The lower 128 bytes of RAM (see Figure 2) are accessible from address 00h to

21T89C51AC2Rev. B – 19-Dec-017.2 External Space7.2.1 Memory Interface The external memory interface comprises the external bus (port 0 and port 2) as

22T89C51AC2Rev. B – 19-Dec-01For simplicity, the accompanying figures depict the bus cycle waveforms in idealizedform and do not provide precise timin

23T89C51AC2Rev. B – 19-Dec-017.3 Dual Data Pointer The T89C51AC2 implements a second data pointer for speeding up code execution andreducing code size

24T89C51AC2Rev. B – 19-Dec-017.4 Registers Table 3. PSW RegisterPSW (S:8Eh)Program Status Word Register.Reset Value= 0000 0000bTable 4. AUXR RegisterA

25T89C51AC2Rev. B – 19-Dec-01Reset Value= X00X 1100bNot bit addressableTable 5. AUXR1 RegisterAUXR1 (S:A2h)Auxiliary Control Register 1.Reset Value= X

26T89C51AC2Rev. B – 19-Dec-018. EEPROM DataMemoryThe 2k byte on-chip EEPROM memory block is located at addresses 0000h to 07FFh ofthe XRAM/ERAM memory

27T89C51AC2Rev. B – 19-Dec-018.4 Examples ;*F*************************************************************************;* NAME: api_rd_eeprom_byte;* DP

28T89C51AC2Rev. B – 19-Dec-018.5 Registers Table 6. EECON RegisterEECON (S:0D2h)EEPROM Control RegisterReset Value= XXXX XX00bNot bit addressable76543

29T89C51AC2Rev. B – 19-Dec-019. Program/CodeMemoryThe T89C51AC2 implement 32 Kbytes of on-chip program/code memory. Figure 8shows the partitioning of

3T89C51AC2Rev. B – 19-Dec-014. Pin ConfigurationPLCC44P1.3 / AN3 / CEX0P1.2 / AN2 / ECIP1.1 / AN1 / T2EXP1.0 / AN 0 / T2VAREFVAGNDRESETVSSVCCXTAL1XTAL

30T89C51AC2Rev. B – 19-Dec-01Figure 9. External Code Memory Interface StructureTable 7. External Code Memory Interface Signals9.1.2 External Bus Cycle

31T89C51AC2Rev. B – 19-Dec-01Figure 10. External Code Fetch Waveforms9.2 FLASH MemoryArchitectureT89C51AC2 features two on-chip flash memories:• Flash

32T89C51AC2Rev. B – 19-Dec-019.2.1 FM0 MemoryArchitectureThe flash memory is made up of 4 blocks (see Figure 11):3. The memory array (user space) 32 K

33T89C51AC2Rev. B – 19-Dec-019.3 Overview of FM0operationsThe CPU interfaces to the flash memory through the FCON register and AUXR1register.These reg

34T89C51AC2Rev. B – 19-Dec-01Table 10. Programming spacesNote: The sequence 5xh and Axh must be executing without instructions between them other-wise

35T89C51AC2Rev. B – 19-Dec-01Figure 12. Column Latches Loading ProcedureNote: The last page address used when loading the column latch is the one used

36T89C51AC2Rev. B – 19-Dec-01• Launch the programming by writing the data sequence 52h followed by A2h inFCON register (only from FM1).The end of the

37T89C51AC2Rev. B – 19-Dec-01Figure 14. Hardware Programming Procedure9.3.7 Reading the FLASHSpacesUser The following procedure is used to read the Us

38T89C51AC2Rev. B – 19-Dec-01Figure 15. Reading Procedure9.3.8 Flash Protection fromParallel ProgrammingThe three lock bits in Hardware Security Byte

39T89C51AC2Rev. B – 19-Dec-019.4 RegistersFCON RegisterFCON (S:D1h)FLASH Control RegisterReset Value= 0000 0000b76543210FPL3 FPL2 FPL1 FPL0 FPS FMOD1

4T89C51AC2Rev. B – 19-Dec-01Table 1. Pin DescriptionPin Name Type DescriptionVSS GND Circuit ground.VCC Supply Voltage.VAREF Reference Voltage for ADC

40T89C51AC2Rev. B – 19-Dec-0110. In-System-Programming (ISP)With the implementation of the User Space (FM0) and the Boot Space (FM1) in Flashtechnolog

41T89C51AC2Rev. B – 19-Dec-0110.2 Boot Process10.2.1 Software boot processexampleMany algorithms can be used for the software boot process. Before des

42T89C51AC2Rev. B – 19-Dec-01Figure 17. Hardware Boot Process Algorithm10.3 Application-Programming-InterfaceSeveral Application Program Interface (AP

43T89C51AC2Rev. B – 19-Dec-01Table 12. List of API10.4 XROW Bytes Table 13. Xrow mappingAPI CALL DescriptionPROGRAM DATA BYTE Write a byte in flash me

44T89C51AC2Rev. B – 19-Dec-0110.5 Hardware SecurityByteTable 14. Hardware Security byteDefault value after erasing chip: FFhNote: Only the 4 MSB bits

45T89C51AC2Rev. B – 19-Dec-0111. Serial I/O Port The T89C51AC2 I/O serial port is compatible with the I/O serial port in the 80C52.It provides both sy

46T89C51AC2Rev. B – 19-Dec-01valid stop bits cannot clear the FE bit. When the FE feature is enabled, RI rises on thestop bit instead of the last data

47T89C51AC2Rev. B – 19-Dec-01more slaves at a time. The following example illustrates how a given address is formed.To address a device by its individ

48T89C51AC2Rev. B – 19-Dec-0111.5 Registers Table 15. SCON RegisterSCON (S:98h)Serial Control RegisterReset Value = 0000 0000bBit addressable76543210F

49T89C51AC2Rev. B – 19-Dec-01Table 16. SADEN RegisterSADEN (S:B9h)Slave Address Mask RegisterReset Value = 0000 0000bNot bit addressableTable 17. SADD

5T89C51AC2Rev. B – 19-Dec-01P2.0:7 I/OPort 2:Is an 8-bit bi-directional I/O port with internal pull-ups. Port 2 pins that have 1’s written to them are

50T89C51AC2Rev. B – 19-Dec-01Table 19. PCON RegisterPCON (S:87h)Power Control RegisterReset Value = 00X1 0000bNot bit addressable76543210SMOD1 SMOD0 -

51T89C51AC2Rev. B – 19-Dec-0112. Timers/Counters The T89C51AC2 implements two general-purpose, 16-bit Timers/Counters. Such areidentified as Timer 0 a

52T89C51AC2Rev. B – 19-Dec-01Figure 22. Timer/Counter x (x= 0 or 1) in Mode 012.2.2 Mode 1 (16-bit Timer) Mode 1 configures Timer 0 as a 16-bit Timer

53T89C51AC2Rev. B – 19-Dec-0112.2.4 Mode 3 (Two 8-bitTimers)Mode 3 configures Timer 0 such that registers TL0 and TH0 operate as separate 8-bitTimers

54T89C51AC2Rev. B – 19-Dec-0112.3.1 Mode 0 (13-bit Timer) Mode 0 configures Timer 1 as a 13-bit Timer, which is set up as an 8-bit Timer (TH1 reg-iste

55T89C51AC2Rev. B – 19-Dec-0112.5 Registers Table 20. TCON RegisterTCON (S:88h)Timer/Counter Control RegisterReset Value= 0000 0000b76543210TF1 TR1 TF

56T89C51AC2Rev. B – 19-Dec-01Table 21. TMOD RegisterTMOD (S:89h)Timer/Counter Mode ControlRegister.Reset Value= 0000 0000b76543210GATE1 C/T1# M11 M01

57T89C51AC2Rev. B – 19-Dec-01Table 22. TH0 RegisterTH0 (S:8Ch)Timer 0 High Byte RegisterReset Value= 0000 0000bTable 23. TL0 RegisterTL0 (S:8Ah)Timer

58T89C51AC2Rev. B – 19-Dec-01Table 25. TL1 RegisterTL1 (S:8Bh)Timer 1 Low Byte RegisterReset Value= 0000 0000b76543210BitNumberBitMnemonic Description

59T89C51AC2Rev. B – 19-Dec-0113. Timer 2 The T89C51AC2 timer 2 is compatible with timer 2 in the 80C52.It is a 16-bit timer/counter: the count is main

6T89C51AC2Rev. B – 19-Dec-014.1 I/O Configurations Each Port SFR operates via type-D latches, as illustrated in Figure 1 for Ports 3 and 4. ACPU "

60T89C51AC2Rev. B – 19-Dec-01Figure 27. Auto-Reload Mode Up/Down Counter13.2 ProgrammableClock-OutputIn clock-out mode, timer 2 operates as a 50%-duty

61T89C51AC2Rev. B – 19-Dec-01It is possible to use timer 2 as a baud rate generator and a clock generator simulta-neously. For this configuration, the

62T89C51AC2Rev. B – 19-Dec-0113.3 Registers Table 26. T2CON RegisterT2CON (S:C8h)Timer 2 Control RegisterReset Value = 0000 0000bBit addressable765432

63T89C51AC2Rev. B – 19-Dec-01Table 27. T2MOD RegisterT2MOD (S:C9h)Timer 2 Mode Control RegisterReset Value = XXXX XX00bNot bit addressableTable 28. TH

64T89C51AC2Rev. B – 19-Dec-01Table 29. TL2 RegisterTL2 (S:CCh)Timer 2 Low Byte RegisterReset Value = 0000 0000bNot bit addressableTable 30. RCAP2H Reg

65T89C51AC2Rev. B – 19-Dec-0114. WatchDog Timer T89C51AC2 contains a powerful programmable hardware WatchDog Timer (WDT) thatautomatically resets the

66T89C51AC2Rev. B – 19-Dec-0114.1 WatchDogProgrammingThe three lower bits (S0, S1, S2) located into WDTPRG register permit to program theWDT duration.

67T89C51AC2Rev. B – 19-Dec-0114.2 WatchDog Timerduring Power downmode and IdleIn Power Down mode the oscillator stops, which means the WDT also stops.

68T89C51AC2Rev. B – 19-Dec-01Table 35. WDTRST RegisterWDTRST (S:A6h Write only)WatchDog Timer Enable registerReset Value = 1111 1111bNote: The WDRST r

69T89C51AC2Rev. B – 19-Dec-0115. ProgrammableCounter Array PCAThe PCA provides more timing capabilities with less CPU intervention than the standardti

7T89C51AC2Rev. B – 19-Dec-01Figure 1. Port 1, Port 3 and Port 4 StructureNote: The internal pull-up can be disabled on P1 when analog function is sele

70T89C51AC2Rev. B – 19-Dec-01Figure 30. PCA Timer/CounterThe CMOD register includes three additional bits associated with the PCA.• The CIDL bit which

71T89C51AC2Rev. B – 19-Dec-01Each module in the PCA has a special function register associated with it (CCAPM0 formodule 0 ...). The CCAPM0:4 register

72T89C51AC2Rev. B – 19-Dec-01Figure 32. PCA Capture Mode15.5 16-bit SoftwareTimer ModeThe PCA modules can be used as software timers by setting both t

73T89C51AC2Rev. B – 19-Dec-0115.6 High Speed OutputModeIn this mode the CEX output (on port 1) associated with the PCA module will toggleeach time a m

74T89C51AC2Rev. B – 19-Dec-01Figure 35. PCA PWM Mode15.8 PCA WatchdogTimerAn on-board watchdog timer is available with the PCA to improve system relia

75T89C51AC2Rev. B – 19-Dec-0115.9 PCA Registers Table 36. CMOD RegisterCMOD (S:D8h)PCA Counter Mode RegisterReset Value = 00XX X000b76543210CIDL WDTE

76T89C51AC2Rev. B – 19-Dec-01Table 37. CCON RegisterCCON (S:D8h)PCA Counter Control RegisterReset Value = 00X0 0000b76543210CF CR - CCF4 CCF3 CCF2 CCF

77T89C51AC2Rev. B – 19-Dec-01Table 38. CCAPnH RegistersCCAP0H (S:FAh)CCAP1H (S:FBh)CCAP2H (S:FCh)CCAP3H (S:FDh)CCAP4H (S:FEh)PCA High ByteCompare/Capt

78T89C51AC2Rev. B – 19-Dec-01Table 40. CCAPMn RegistersCCAPM0 (S:DAh)CCAPM1 (S:DBh)CCAPM2 (S:DCh)CCAPM3 (S:DDh)CCAPM4 (S:DEh)PCA Compare/Capture Modul

79T89C51AC2Rev. B – 19-Dec-01Table 41. CH RegisterCH (S:F9h)PCA Counter Register HighvalueReset Value = 0000 00000bTable 42. CL RegisterCL (S:E9h)PCA

8T89C51AC2Rev. B – 19-Dec-01Figure 3. Port 2 StructureNotes: 1. Port 2 is precluded from use as general purpose I/O Ports when as address/data busdriv

80T89C51AC2Rev. B – 19-Dec-0116. Analog-to-DigitalConverter (ADC)This section describes the on-chip 10 bit analog-to-digital converter of the T89C51AC

81T89C51AC2Rev. B – 19-Dec-01Figure 36. ADC DescriptionFigure 37 shows the timing diagram of a complete conversion. For simplicity, the figuredepicts

82T89C51AC2Rev. B – 19-Dec-0116.3 ADC ConverterOperationA start of single A/D conversion is triggered by setting bit ADSST (ADCON.3).After completion

83T89C51AC2Rev. B – 19-Dec-0116.6 ADC Standby Mode When the ADC is not used, it is possible to set it in standby mode by clearing bit ADENin ADCON reg

84T89C51AC2Rev. B – 19-Dec-0116.9 Registers Table 44. ADCF RegisterADCF (S:F6h)ADC ConfigurationReset Value=0000 0000bTable 45. ADCON RegisterADCON (S

85T89C51AC2Rev. B – 19-Dec-01Table 46. ADCLK RegisterADCLK (S:F2h)ADC Clock PrescalerReset Value: XXX0 0000bTable 47. ADDH RegisterADDH (S:F5h Read On

86T89C51AC2Rev. B – 19-Dec-0117. Interrupt System The controller has a total of 8 interrupt vectors: two external interrupts (INT0 and INT1),three tim

87T89C51AC2Rev. B – 19-Dec-01Each of the interrupt sources can be individually enabled or disabled by setting or clear-ing a bit in the Interrupt Enab

88T89C51AC2Rev. B – 19-Dec-0117.1 Registers Table 51. IEN0 RegisterIEN0 (S:A8h)Interrupt Enable RegisterReset Value: 0000 0000bbit addressable76543210

89T89C51AC2Rev. B – 19-Dec-01Table 52. IEN1 RegisterIEN1 (S:E8h)Interrupt Enable RegisterReset Value: xxxx x000bbit addressable76543210---- -EADC-BitN

9T89C51AC2Rev. B – 19-Dec-01It is not obvious the last three instructions in this list are Read-Modify-Write instructions.These instructions read the

90T89C51AC2Rev. B – 19-Dec-01Table 53. IPL0 RegisterIPL0 (S:B8h)Interrupt Enable RegisterReset Value: X000 0000bbit addressable76543210- PPC PT2 PS PT

91T89C51AC2Rev. B – 19-Dec-01Table 54. IPL1 RegisterIPL1 (S:F8h)Interrupt Priority Low Register 1Reset Value: XXXX X000bbit addressable76543210- - - -

92T89C51AC2Rev. B – 19-Dec-01Table 55. IPL0 RegisterIPH0 (B7h)Interrupt High Priority RegisterReset Value: X000 0000b76543210- PPCH PT2H PSH PT1H PX1H

93T89C51AC2Rev. B – 19-Dec-01Table 56. IPH1 RegisterIPH1 (S:FFh)Interrupt high priority Register 1Reset Value = XXXX X000b76543210- - - - - PADCH -Bit

94T89C51AC2Rev. B – 19-Dec-0118. Electrical Characteristics18.1 Absolute MaximumRatings(1)18.2 DC Parameters for Standard VoltageTA =-40°Cto+85°C; VSS

95T89C51AC2Rev. B – 19-Dec-01Notes: 1. Operating ICCis measured with all output pins disconnected; XTAL1 driven withTCLCH,TCHCL= 5 ns (see Figure 44.)

96T89C51AC2Rev. B – 19-Dec-01Figure 41. ICCTest Condition, Active ModeFigure 42. ICCTest Condition, Idle ModeFigure 43. ICCTest Condition, Power-Down

97T89C51AC2Rev. B – 19-Dec-01Figure 44. Clock Signal Waveform for ICCTests in Active and Idle Modes18.3 DC Parameters for A/D ConverterTable 58. DC Pa

98T89C51AC2Rev. B – 19-Dec-0118.4.2 External ProgramMemory Characteristics Table 59. Symbol DescriptionTable 60. AC Parameters for a Fix Clock (F= 40

99T89C51AC2Rev. B – 19-Dec-01Table 61. AC Parameters for a Variable Clock18.4.3 External ProgramMemory Read CycleSymbol TypeStandardClock X2 Clock X p