
MAX5290–MAX5295
Buffered, Fast-Settling, Dual, 12-/10-/8-Bit,
Voltage-Output DACs
______________________________________________________________________________________ 19
CONTROL BITS DATA BITS
DATA
C3 C2 C1 C0
D1 D1
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
FUNCTION
SELECT BITS
DIN 111000XX X X X X X X MB MA
Load DAC register A from
input register A when MA
is 1. DAC register A is
unchanged if MA is 0.
Load DAC register B from
input register B when MB
is 1. DAC register B is
unchanged if MB is 0.
SHUTDOWN-MODE BITS
DIN 1 1 1 0 0 1 0 X X X X X PDB1 PDB0 PDA1 PDA0
Write DACA and DACB
shutdown mode bits. See
Table 8.
DIN1110011XXXXXXXXX
DOUTRB X X X X X X X X X X X X PDB1 PDB0 PDA1 PDA0
Read DACA and DACB
shutdown mode bits.
UPIO CONFIGURATION BITS
DIN 1 1 1 0 1 0 0 X UPSL2 UPSL1 UP3 UP2 UP1 UP0 X X
Write UPIO configuration
bits. See Tables 19 and
22.
DIN1110101XXXXXXXXX
DOUTRB X X X X X X X X UP3-2 UP2-2 UP1-2 UP0-2 UP3-1 UP2-1 UP1-1 UP0-1
Read UPIO configuration
bits.
SETTLING-TIME-MODE BITS
DIN 1 1 1 0 1 1 0 X X X X X X X SPDB SPDA
Write DACA and DACB
settling-time mode bits.
DIN1110111XXXXXXXXX
DOUTRB X X X X X X X X X X X X X X SPDB SPDA
Read DACA and DACB
settling-time mode bits.
CPOL AND CPHA CONTROL BITS
DIN 1 1 1 1 0 0 0 0 X X X X X X CPOL CPHA
Write CPOL, CPHA control
bits. See Table 15.
DIN 11110001 X X X X X X X X
DOUTRB X X X X X X X X X X X X X X CPOL CPHA
Read CPOL, CPHA control
bits.
Table 2b. Advanced-Feature Programming Commands
X = Don’t care.
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