Rainbow-electronics MAX19515 Manual do Utilizador descarregar pdf (Página 24)

Clock Inputs

The input clock interface provides for flexibility in the

requirements of the clock driver. The MAX19515

accepts a fully differential clock or single-ended logic-

level clock. For differential clock operation, connect a

differential clock to the CLK+ and CLK- inputs. In this

mode, the input common mode is established internally

to allow for AC-coupling. The differential clock signal

can also be DC-coupled if the common mode is con-

strained to the specified 1V to 1.4V clock input com-

mon-mode range. For single-ended operation, connect

CLK- to GND and drive the CLK+ input with a logic-

level signal. When the CLK- input is grounded (or

pulled below the threshold of the clock mode detection

comparator) the differential-to-single-ended conversion

stage is disabled and the logic-level inverter path is

activated.

Clock Divider

The MAX19515 offers a clock-divider option. Enable

clock division either by setting DIV0 and DIV1 through

the serial interface; see the Clock Divide/Data

MAX19515

Dual-Channel, 10-Bit, 65Msps ADC

24 ______________________________________________________________________________________

CLK+

100Ω

TERMINATION

(PROGRAMMABLE)

SELF-BIAS TURNED OFF FOR

SINGLE-ENDED CLOCK

OR POWER-DOWN.

CLK-

GND

AVDD

10kΩ

20kΩ

5kΩ

50Ω

2:1 MUX

SELECT

THRESHOLD

Figure 8. Simplified Clock Input Schematic

DCLK

DATA, DOR

SAMPLE CLOCK

n n+1

SAMPLE ON RISING EDGE

n+2 n+4 n+5

n-9 n-8n-10 n-7 n-6 n-5 n-4

CLK

SETUP

HOLD

DUAL-BUS OUTPUT MODE

SAMPLE CLOCK IS THE DERIVED CLOCK FROM (CLK+ - CLK-)/CLOCK DIVIDER, IN_ = IN_+ - IN_-.

SAMPLING

INSTANT

SAMPLING

INSTANT

SAMPLING

INSTANT

SAMPLING

INSTANT

SAMPLING

INSTANT

SAMPLING

INSTANT

IN_

n+3

Figure 9. Dual-Bus Output Mode Timing

1 2 ... 19 20 21 22 23 24 25 26 27 28 29 ... 33 34

MAX19515 1

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