MAX1778/MAX1880–MAX1885
Quad-Output TFT LCD DC-DC
Converters with Buffer
32 ______________________________________________________________________________________
regulator and charge-pump power ground plane,
and the inner layer should contain the analog
ground plane and power-ground plane/path for the
V
COM
buffer and LDO. Connect all three ground
planes together at one place near the PGND pin.
3) Locate all feedback resistive-dividers as close to
their respective feedback pins as possible. The
voltage-divider’s center trace should be kept short.
Avoid running any feedback trace near the LX
switching node or the charge-pump drivers. The
resistive-dividers’ ground connections should be to
analog ground (GND).
4) When using multilayer boards, separate the top sig-
nal layer and bottom signal layer with a ground
plane between to eliminate capacitive coupling
between fast-charging nodes on the top layer and
high-impedance nodes on the bottom layer. The
fast-charging nodes, such as the LX and charge-
pump driver nodes, should not have any other
traces or ground planes near by.
5) Keep the charge-pump circuitry as close to the IC
as possible, using wide traces and avoiding vias
when possible. Place 0.1µF ceramic bypass
capacitors near the charge-pump input pins (SUPP
and SUPN) to the PGND pin.
6) To maximize output power and efficiency and mini-
mize output ripple voltage, use extra wide, power
ground traces, and solder the IC’s power ground
pin directly to it.
Refer to the MAX1778/MAX1880-MAX1885 evaluation
kit for an example of proper board layout.
Comentários a estes Manuais