MAX11043
4-Channel, 16-Bit, Simultaneous-Sampling ADCs
with PGA, Filter, and 8-/12-Bit Dual-Stage DAC
20 ______________________________________________________________________________________
SCHAN_<4:1>: Automatic ADC result output for each
channel (A, B, C, and D).
1 = ADC channel data is output on DOUT each time a
new result is valid in the sequence, A, B, C, and D.
0 = ADC data is not presented automatically for this
channel (default).
When SCHAN_ = 1, the selected ADC channel data is
automatically presented on DOUT each time EOC
asserts low in the sequence A, B, C, and D with the
unselected channels omitted. The data transitions on
the rising edge of SCLK. Force CS low to initiate trans-
mission. CS can go high between results. The MSB of
the first selected ADC channel outputs immediately
after the falling edge of EOC. EOC goes high after the
last bit of the selected channels clocks out or one clock
cycle before the next result is ready. Insufficient SCLK
pulses result in truncated data. Extra clock pulses give
an undefined output. In scan mode, keep DIN high or
write data to the MAX11043 as usual. In scan mode,
the MAX11043 ignores requests for data reads.
DECSEL<0>: Decimate select.
1 = decimate by 12.
0 = decimate by 24 (default).
Set DECSEL high to decimate the ADC result by 12,
doubling the number of samples. The SPI interface is
limited to 40Mbps.
BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8
X X X X DAC11 DAC10 DAC9 DAC8
Fine DAC Register (09h)
X<15:12>: Don’t-care bits.
DAC_<11:0>: Contains current fine DAC output value.
When using the DACSTEP input to change the DAC
value, this register updates to the new value on the
next rising edge of the system clock following the rising
edge of DACSTEP. The power-on default is 0.
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
DAC7 DAC6 DAC5 DAC4 DAC3 DAC2 DAC1 DAC0
BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8
X X X X DACSTEP11 DACSTEP10 DACSTEP9 DACSTEP8
DACSTEP Register (0Ah)
X<15:12>: Don’t-care bits.
DACSTEP11:DACSTEP0<11:0>: Provides the size of
the DAC step. The value is positive only and the
UP/DWN input is used to set the direction. The value in
the fine DAC register updates on the next rising edge
of the system clock following the rising edge of the
DACSTEP input. The power-on default is 0.
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
DACSTEP7 DACSTEP6 DACSTEP5 DACSTEP4 DACSTEP3 DACSTEP2 DACSTEP1 DACSTEP0
BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8
DACH7 DACH6 DACH5 DACH4 DACH3 DACH2 DACH1 DACH0
Coarse DACH/DACL Register (0Bh)
DACH7:DACH0<15:8>: High coarse DAC value.
DACL7:DACL0<7:0>: Low coarse DAC value.
Coarse DAC sets high and low references for the fine
DAC. The power-on default is 0.
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
DACL7 DACL6 DACL5 DACL4 DACL3 DACL2 DACL1 DACL0
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