Rainbow-electronics MAX106 Manual do Utilizador descarregar pdf (Página 5)

MAX106

±5V, 600Msps, 8-Bit ADC with On-Chip

2.2GHz Bandwidth Track/Hold Amplifier

_______________________________________________________________________________________ 5

CONDITIONS UNITSMIN TYP MAXSYMBOLPARAMETER

20% to 80%, C

= 3pF

20% to 80%, C

= 3pF

20% to 80%, C

= 3pF

Figure 17

Figure 15

Figure 4

Figure 17

ps220t

RDREADY

DREADY Rise Time

ps360t

FDATA

DATA Fall Time

ps420t

RDATA

DATA Rise Time

ps-50 150 350t

PD2

DREADY to DATA Propagation

Delay (Note 14)

ns2.2t

PD1

CLK to DREADY Propagation

Delay

ps0t

Reset Input Data Hold Time

(Note 13)

ps0t

Reset Input Data Setup Time

(Note 13)

ps< 0.5t

Aperture Jitter

ps100t

Aperture Delay

DIV1, DIV2 modes

20% to 80%, C

= 3pF

9.5

Clock

Cycles

8.5

PDA

Auxiliary Port Pipeline Delay

Clock

Cycles

7.5

PDP

Primary Port Pipeline Delay

ps180t

FDREADY

DREADY Fall Time

AC ELECTRICAL CHARACTERISTICS (continued)

A = V

I = V

D = +5.0V, V

= -5.0V, V

O = +3.3V, REFIN connected to REFOUT, f

= 600Msps, f

at -1dBFS, T

= +25°C,

unless otherwise noted.)

Note 1: Static linearity parameters are computed from a “best-fit” straight line through the code transition points. The full-scale

range (FSR) is defined as 256

· slope of the line.

Note 2: The offset control input is a self-biased voltage divider from the internal +2.5V reference voltage. The nominal open-circuit

voltage is +1.25V. It may be driven from an external potentiometer connected between REFOUT and GNDI.

Note 3: The clock input’s termination voltage can be operated between -2.0V and GNDI. Observe the absolute maximum ratings on

the CLK+ and CLK- inputs.

Note 4: Input logic levels are measured with respect to the V

O power-supply voltage.

Note 5: All PECL digital outputs are loaded with 50Ω to V

O - 2.0V. Measurements are made with respect to the V

O power-

supply voltage.

Note 6: The current in the V

O power supply does not include the current in the digital output’s emitter followers, which is a func-

tion of the load resistance and the V

termination voltage.

Note 7: Common-mode rejection ratio is defined as the ratio of the change in the transfer-curve offset voltage to the change in the

common-mode voltage, expressed in dB.

Note 8: Measured with the positive supplies tied to the same potential, V

A = V

D = V

I. V

varies from +4.75V to +5.25V.

Note 9: V

varies from -5.25V to -4.75V.

Note 10: Power-supply rejection ratio is defined as the ratio of the change in the transfer-curve offset voltage to the change in power

supply voltage, expressed in dB.

Note 11: Effective number of bits (ENOB) are computed from a curve fit referenced to the theoretical full-scale range.

7.5

Msps600f

MAX

Maximum Sample Rate

Figure 17 ns0.75t

PWL

Clock Pulse Width Low

Figure 17 ns0.75 5t

PWH

Clock Pulse Width High

TIMING CHARACTERISTICS

Figures 6, 7, and 8

DIV4 mode

1 2 3 4 5 6 7 8 9 10 ... 30 31

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