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MAX106

±5V, 600Msps, 8-Bit ADC with On-Chip

2.2GHz Bandwidth Track/Hold Amplifier

20 ______________________________________________________________________________________

AC-Coupling Clock Inputs

The clock inputs CLK+ and CLK- can also be driven

with positive referenced ECL (PECL) logic levels if the

clock inputs are AC-coupled. Under this condition, con-

nect CLKCOM to GNDI. Single-ended ECL/PECL/sine-

wave drive is also possible if the undriven clock input is

reverse-terminated to GNDI through a 50Ω resistor in

series with a capacitor whose value is identical to that

used to couple the driven input.

Demux Reset Operation

The MAX106 features an internal 1:2 demultiplexer that

reduces the data rate of the output digital data to one-

half the sample clock rate. Demux reset is necessary

when interleaving multiple MAX106s and/or synchroniz-

ing external demultiplexers. The simplified block dia-

gram of Figure 1 shows that the demux reset signal path

consists of four main circuit blocks. From input to out-

put, they are the reset input dual latch, the reset

pipeline, the demux clock generator, and the reset out-

put. The signals associated with the demux reset opera-

tion and the control of this section are listed in Table 6.

Reset Input Dual Latch

The reset input dual-latch circuit block accepts differ-

ential PECL reset inputs referenced to the same V

power supply that powers the MAX106 PECL outputs.

For applications that do not require a synchronizing

reset, the reset inputs can be left open. In this case,

they will self-bias to a proper level with internal 50kΩ

resistors and a 20µA current source. This combination

creates a -1V difference between RSTIN+ and RSTIN-

to disable the internal reset circuitry. When driven with

PECL logic levels terminated with 50Ω to (V

O - 2V),

the internal biasing network can easily be overdriven.

Figure 14 shows a simplified schematic of the reset

input structure.

To properly latch the reset input data, setup (t

) and

data-hold times (t

) must be met with respect to the

rising edge of the sample clock. The timing diagram of

Figure 15 shows the timing relationship of the reset

input and sampling clock.

Table 5. DC-Coupled Clock Drive Options

-10dBm to +4dBm Figure 13aSingle-Ended Sine Wave

CLK+

GNDI

CLKCOMCLOCK DRIVE REFERENCE

External 50Ω to GNDI

CLK-

-10dBm to +4dBm -10dBm to +4dBm Figure 13bDifferential Sine Wave GNDI

ECL Drive -1.3V Figure 13cSingle-Ended ECL -2V

ECL Drive

Figure 13dDifferential ECL -2V

50k50k

RSTIN+

RSTIN-

RESET INPUTS ARE ESD PROTECTED

(NOT SHOWN ON THIS SIMPLIFIED DRAWING).

20µA

GNDD

Figure 14. Simplified Reset Input Structure

RSTIN+

50% 50%

CLK+

CLK-

RSTIN-

50%

Figure 15. Reset Input Timing Definitions

1 2 ... 15 16 17 18 19 20 21 22 23 24 25 ... 30 31

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