
MAX100
250Msps, 8-Bit ADC with Track/Hold
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CLK
AData
BData
CLK
DCLK
DCLK
t
pd1
t
pd2
t
pwh
t
pwl
Figure 2. Output Timing: Divide-by-2 or Divide-by-5 Mode (DIV = 1)
AData
BData
CLK
DCLK
t
pd1
t
pd2
t
NPD
12345678
N - 1 N N + 1
N - 1 N N + 1
N - 1 N N + 1
Figure 3. Output Timing: Clock to Data, Divide-by-1 Mode (fast mode, DIV = 0)
AData
BData
CLK
DCLK
t
pd2
t
NPD
N - 1 N + 3
N - 2 N N + 2
N - 1 N N + 1
N + 2N - 2
12345
N + 1
Figure 4. Output Timing: Divide-by-2 Mode (DIV = 1)
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