102
8209A–AVR–08/09
ATmega16M1/32M1/64M1
• Bit 2 – OCIE0B: Timer/Counter Output Compare Match B Interrupt Enable
When the OCIE0B bit is written to one, and the I-bit in the Status Register is set, the
Timer/Counter Compare Match B interrupt is enabled. The corresponding interrupt is executed if
a Compare Match in Timer/Counter occurs, i.e., when the OCF0B bit is set in the “TIFR0 –
Timer/Counter 0 Interrupt Flag Register” on page 102.
• Bit 1 – OCIE0A: Timer/Counter0 Output Compare Match A Interrupt Enable
When the OCIE0A bit is written to one, and the I-bit in the Status Register is set, the
Timer/Counter0 Compare Match A interrupt is enabled. The corresponding interrupt is executed
if a Compare Match in Timer/Counter0 occurs, i.e., when the OCF0A bit is set in the “TIFR0 –
Timer/Counter 0 Interrupt Flag Register” on page 102.
• Bit 0 – TOIE0: Timer/Counter0 Overflow Interrupt Enable
When the TOIE0 bit is written to one, and the I-bit in the Status Register is set, the
Timer/Counter0 Overflow interrupt is enabled. The corresponding interrupt is executed if an
overflow in Timer/Counter0 occurs, i.e., when the TOV0 bit is set in the “TIFR0 – Timer/Counter
0 Interrupt Flag Register” on page 102.
15.9.7 TIFR0 – Timer/Counter 0 Interrupt Flag Register
• Bits 7:3 – Res: Reserved Bits
These bits are reserved and will always read as zero.
• Bit 2 – OCF0B: Timer/Counter 0 Output Compare B Match Flag
The OCF0B bit is set when a Compare Match occurs between the Timer/Counter and the data in
“OCR0B – Output Compare Register B” on page 101. OCF0B is cleared by hardware when exe-
cuting the corresponding interrupt handling vector. Alternatively, OCF0B is cleared by writing a
logic one to the flag. When the I-bit in SREG, OCIE0B (Timer/Counter Compare B Match Inter-
rupt Enable), and OCF0B are set, the Timer/Counter Compare Match Interrupt is executed.
• Bit 1 – OCF0A: Timer/Counter 0 Output Compare A Match Flag
The OCF0A bit is set when a Compare Match occurs between the Timer/Counter0 and the data
in “OCR0A – Output Compare Register A” on page 101. OCF0A is cleared by hardware when
executing the corresponding interrupt handling vector. Alternatively, OCF0A is cleared by writing
a logic one to the flag. When the I-bit in SREG, OCIE0A (Timer/Counter0 Compare Match Inter-
rupt Enable), and OCF0A are set, the Timer/Counter0 Compare Match Interrupt is executed.
• Bit 0 – TOV0: Timer/Counter0 Overflow Flag
The bit TOV0 is set when an overflow occurs in Timer/Counter0. TOV0 is cleared by hardware
when executing the corresponding interrupt handling vector. Alternatively, TOV0 is cleared by
writing a logic one to the flag. When the SREG I-bit, TOIE0 (Timer/Counter0 Overflow Interrupt
Enable), and TOV0 are set, the Timer/Counter0 Overflow interrupt is executed.
The setting of this flag is dependent of the WGM02:0 bit setting. Refer to Table 15-8, “Waveform
Generation Mode Bit Description” on page 99.
Bit 76543210
–––––OCF0BOCF0ATOV0TIFR0
Read/Write RRRRRR/WR/WR/W
Initial Value00000000
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