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163

ATmega16(L)

2466B–09/01

Two-wire Serial

Interface

Features • Simple Yet Powerful and Flexible Communication Interface, Only two Bus Lines Needed

• Both Master and Slave Operation Supported

• Device can Operate as Transmitter or Receiver

• 7-bit Address Space allows up to 128 Different Slave Addresses

• Multi-master Arbitration Support

• Up to 400 kHz Data Transfer Speed

• Slew-rate Limited Output Drivers

• Noise Suppression Circuitry Rejects Spikes on Bus Lines

• Fully Programmable Slave Address with General Call Support

• Address Recognition causes Wake-up when AVR is in Sleep Mode

Two-wire Serial Interface

Bus Definition

The Two-Wire Serial Interface (TWI) is ideally suited for typical microcontroller applica-

tions. The TWI protocol allows the systems designer to interconnect up to 128 different

devices using only two bidirectional bus lines, one for clock (SCL) and one for data

(SDA). The only external hardware needed to implement the bus is a single pull-up

resistor for each of the TWI bus lines. All devices connected to the bus have individual

addresses, and mechanisms for resolving bus contention are inherent in the TWI

protocol.

Figure 76. TWI Bus Interconnection

TWI Terminology The following definitions are frequently encountered in this section.

Device 1

Device 2

Device 3

Device n

SDA

SCL

........

R1 R2

Table 72. TWI Terminology

Term Description

Master The device that initiates and terminates a transmission. The master also

generates the SCL clock

Slave The device addressed by a master

Transmitter The device placing data on the bus

Receiver The device reading data from the bus

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