Rainbow-electronics Atmega169L Manual do Utilizador descarregar pdf (Página 150)

150

ATmega169V/L

2514A–AVR–08/02

USART The Universal Synchronous and Asynchronous serial Receiver and Transmitter

(USART) is a highly flexible serial communication device. The main features are:

•

Full Duplex Operation (Independent Serial Receive and Transmit Registers)

• Asynchronous or Synchronous Operation

• Master or Slave Clocked Synchronous Operation

• High Resolution Baud Rate Generator

• Supports Serial Frames with 5, 6, 7, 8, or 9 Data Bits and 1 or 2 Stop Bits

• Odd or Even Parity Generation and Parity Check Supported by Hardware

• Data OverRun Detection

• Framing Error Detection

• Noise Filtering Includes False Start Bit Detection and Digital Low Pass Filter

• Three Separate Interrupts on TX Complete, TX Data Register Empty and RX Complete

• Multi-processor Communication Mode

• Double Speed Asynchronous Communication Mode

Overview A simplified block diagram of the USART Transmitter is shown in Figure 68. CPU acces-

sible I/O Registers and I/O pins are shown in bold.

Figure 68. USART Block Diagram

(1)

Note: 1. Refer to Figure 1 on page 2, Table 36 on page 64, and Table 30 on page 60 for

USART pin placement.

PARITY

GENERATOR

UBRR[H:L]

UDR (Transmit)

UCSRA UCSRB UCSRC

BAUD RATE GENERATOR

TRANSMIT SHIFT REGISTER

RECEIVE SHIFT REGISTER RxD

TxD

CONTROL

UDR (Receive)

CONTROL

XCK

DATA

RECOVERY

CLOCK

RECOVERY

CONTROL

PARITY

CHECKER

DATA BUS

OSC

SYNC LOGIC

Clock Generator

Transmitter

Receiver

1 2 ... 145 146 147 148 149 150 151 152 153 154 155 ... 316 317

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