
ATmega163(L)
132
Notes: 1. t
WLRH
is valid for the Write EEPROM, Write Fuse Bits and Write Lock Bits commands.
2. t
WLRH_CE
is valid for the Chip Erase command.
3. t
WLRH_FLASH
is valid for the Write Flash command.
Serial Downloading
Both the Flash and EEPROM memory arrays can be programmed using the serial SPI bus while RESET is pulled to GND.
The serial interface consists of pins SCK, MOSI (input) and MISO (output). After RESET
is set low, the Programming
Enable instruction needs to be executed first before program/erase operations can be executed.
Table 58. Parallel Programming Characteristics, T
A
= 25°C ± 10%, V
CC
= 5 V ± 10%
Symbol Parameter Min Typ Max Units
V
PP
Programming Enable Voltage 11.5 12.5 V
I
PP
Programming Enable Current 250 µA
t
DVXH
Data and Control Valid before XTAL1 High 67 ns
t
XHXL
XTAL1 Pulse Width High 67 ns
t
XLDX
Data and Control Hold after XTAL1 Low 67 ns
t
XLWL
XTAL1 Low to WR Low 67 ns
t
BVPH
BS1 Valid before PAGEL High 67 ns
t
PHPL
PAGEL Pulse Width High 67 ns
t
PLBX
BS1 Hold after PAGEL Low 67 ns
t
PLWL
PAGEL Low to WR Low 67 ns
t
BVWL
BS1 Valid to WR Low 67 ns
t
RHBX
BS1 Hold after RDY/BSY High 67 ns
t
WLWH
WR Pulse Width Low 67 ns
t
WLRL
WR Low to RDY/BSY Low 0 2.5 µs
t
WLRH
WR Low to RDY/BSY High
(1)
11.51.9ms
t
WLRH_CE
WR Low to RDY/BSY High for Chip Erase
(2)
16 23 30 ms
t
WLRH_FLASH
WR Low to RDY/BSY High for Write Flash
(3)
81215ms
t
XLOL
XTAL1 Low to OE Low 67 ns
t
OLDV
OE Low to DATA Valid 20 ns
t
OHDZ
OE High to DATA Tri-stated 20 ns
Comentários a estes Manuais