Rainbow-electronics ATmega161L Manual do Utilizador descarregar pdf (Página 125)

125

ATmega161(L)

1228C–AVR–08/02

Notes: 1. t

WLRH

is valid for the Write EEPROM, Write Fuse bits and Write Lock bits commands.

2. t

WLRH_CE

is valid for the Chip Erase command.

3. t

WLRH_FLASH

is valid for the Write Flash command.

Serial Downloading Both the Flash and EEPROM memory arrays can be programmed using the serial SPI

bus while RESET

is pulled to GND. The serial interface consists of pins SCK, MOSI

(input) and MISO (output). After RESET

is set low, the Programming Enable instruction

needs to be executed first, before program/erase operations can be executed.

When programming the EEPROM, an auto-erase cycle is built into the self-timed pro-

gramming operation (in the Serial mode ONLY) and there is no need to first execute the

Chip Erase instruction. The chip erase operation turns the contents of every memory

location in both the program and EEPROM arrays into $FF.

The program and EEPROM memory arrays have separate address spaces:

$0000 to $1FFF for Program memory and $0000 to $01FF for EEPROM memory.

Either an external system clock is supplied at pin XTAL1 or a crystal needs to be con-

nected across pins XTAL1 and XTAL2. The minimum low and high periods for the serial

clock (SCK) input are defined as follows:

Low: > 2 XTAL1 clock cycles

High: > 2 XTAL1 clock cycles

Table 45. Parallel Programming Characteristics, T

=25°C ± 10%, V

=5V±

10%

(1)(2)(3)

Symbol Parameter Min Typ Max Units

Programming Enable Voltage 11.5 12.5 V

Programming Enable Current 250 µA

DVXH

Data and Control Valid before XTAL1 High 67 ns

XHXL

XTAL1 Pulse Width High 67 ns

XLDX

Data and Control Hold after XTAL1 Low 67 ns

XLWL

XTAL1 Low to WR Low 67 ns

BVXH

BS1 Valid before XTAL1 High 67 ns

PHPL

PAGEL Pulse Width High 67 ns

PLBX

BS1 Hold after PAGEL Low 67 ns

PLWL

PAGEL Low to WR Low 67 ns

BVWL

BS1 Valid to WR Low 67 ns

RHBX

BS1 Hold after RDY/BSY High 67 ns

WLWH

WR Pulse Width Low 67 ns

WLRL

WR Low to RDY/BSY Low 0 2.5 µs

WLRH

WR Low to RDY/BSY High

(1)

11.7ms

WLRH_CE

WR Low to RDY/BSY High for Chip Erase

(2)

16 28 ms

WLRH_FLASH

WR Low to RDY/BSY High for Write Flash

(3)

814ms

XLOL

XTAL1 Low to OE Low 67 ns

OLDV

OE Low to DATA Valid 20 ns

OHDZ

OE High to DATA Tri-stated 20 ns

1 2 ... 120 121 122 123 124 125 126 127 128 129 130 ... 158 159

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