Rainbow-electronics ATmega128RFA1 Manual do Utilizador descarregar pdf (Página 223)

223

8266A-MCU Wireless-12/09

ATmega128RFA1

16.2.5 PCICR – Pin Change Interrupt Control Register

Bit 7 6 5 4 3 2 1 0

NA ($68) Res4 Res3 Res2 Res1 Res0 PCIE2 PCIE1 PCIE0 PCICR

Read/Write R R R R R RW RW RW

Initial Value 0 0 0 0 0 0 0 0

• Bit 7:3 – Res4:0 - Reserved Bit

This bit is reserved for future use. A read access always will return zero. A write access

does not modify the content.

• Bit 2 – PCIE2 - Pin Change Interrupt Enable 2

When the PCIE2 bit is set (one) and the I-bit in the Status Register (SREG) is set (one),

pin change interrupt 2 is enabled. Any change on any enabled PCINT23:16 pin will

cause an interrupt. The corresponding interrupt of Pin Change Interrupt Request is

executed from the PCI2 Interrupt Vector. PCINT23:16 pins are enabled individually by

the PCMSK2 Register. Note that the I/O ports corresponding to PCINT23:16 are not

implemented. Therefore PCIE2 has no function in this device.

• Bit 1 – PCIE1 - Pin Change Interrupt Enable 1

When the PCIE1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one),

pin change interrupt 1 is enabled. Any change on any enabled PCINT15:8 pin will

cause an interrupt. The corresponding interrupt of Pin Change Interrupt Request is

executed from the PCI1 Interrupt Vector. PCINT15:8 pins are enabled individually by

the PCMSK1 Register. Note that the I/O ports corresponding to PCINT15:9 are not

implemented.

• Bit 0 – PCIE0 - Pin Change Interrupt Enable 0

When the PCIE0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one),

pin change interrupt 0 is enabled. Any change on any enabled PCINT7:0 pin will cause

an interrupt. The corresponding interrupt of Pin Change Interrupt Request is executed

from the PCI0 Interrupt Vector. PCINT7:0 pins are enabled individually by the PCMSK0

16.2.6 PCIFR – Pin Change Interrupt Flag Register

Bit 7 6 5 4 3 2 1 0

$1B ($3B) Res4 Res3 Res2 Res1 Res0 PCIF2 PCIF1 PCIF0 PCIFR

Read/Write R R R R R RW RW RW

Initial Value 0 0 0 0 0 0 0 0

• Bit 7:3 – Res4:0 - Reserved Bit

This bit is reserved for future use. A read access always will return zero. A write access

does not modify the content.

• Bit 2 – PCIF2 - Pin Change Interrupt Flag 2

When a logic change on any PCINT23:16 pin triggers an interrupt request, PCIF2

becomes set (one). If the I-bit in SREG and the PCIE2 bit in PCICR are set (one), the

MCU will jump to the corresponding Interrupt Vector. The flag is cleared when the

interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical

one to it. Note that the I/O ports corresponding to PCINT23:16 are not implemented.

Therefore PCIF2 has no function in this device.

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