2
6264A–CAP–21-May-07
AT91CAP9S500A/AT91CAP9S250A
– Four 32-bit Battery Backup Registers for a Total of 16 Bytes
– Clock Generator and Power Management Controller
– Advanced Interrupt Controller and Debug Unit
– Periodic Interval Timer, Watchdog Timer and Real-Time Timer
• Reset Controller (RSTC)
– Based on Two Power-on Reset Cells, Reset Source Identification and Reset Output Control
• Shutdown Controller (SHDC)
– Programmable Shutdown Pin Control and Wake-up Circuitry
• Clock Generator (CKGR)
– 32,768 Hz Low-power Oscillator on Battery Backup Power Supply, Providing a Permanent
Slow Clock
– 8 to 16 MHz On-chip Oscillator
– Two PLLs up to 240 MHz
– One USB 480 MHz PLL
• Power Management Controller (PMC)
– Very Slow Clock Operating Mode, Software Programmable Power Optimization Capabilities
– Four Programmable External Clock Signals
• Advanced Interrupt Controller (AIC)
– Individually Maskable, Eight-level Priority, Vectored Interrupt Sources
– Two External Interrupt Sources and One Fast Interrupt Source, Spurious Interrupt Protected
• Debug Unit (DBGU)
– 2-wire UART and Support for Debug Communication Channel, Programmable ICE Access
Prevention
• Periodic Interval Timer (PIT)
– 20-bit Interval Timer plus 12-bit Interval Counter
• Watchdog Timer (WDT)
– Key-protected, Programmable Only Once, Windowed 16-bit Counter Running at Slow Clock
• Real-Time Timer (RTT)
– 32-bit Free-running Backup Counter Running at Slow Clock with 16-bit Prescaler
• Four 32-bit Parallel Input/Output Controllers (PIOA, PIOB, PIOC and PIOE)
– 128 Programmable I/O Lines Multiplexed with up to Two Peripheral I/Os
– Input Change Interrupt Capability on Each I/O Line
– Individually Programmable Open-drain, Pull-up Resistor and Synchronous Output
• DMA Controller (DMAC)
– Acts as one Bus Matrix Master
– Embeds 4 Unidirectional Channels with Programmable Priority, Address Generation, Channel
Buffering and Control
– Supports Four External DMA Requests and Four Internal DMA Requests from the Metal
Programmable Block (MPBlock)
• Twenty-two Peripheral DMA Controller Channels (PDC)
• One 2.0A and 2.0B Compliant CAN Controller
– 16 Fully-programmable Message Object Mailboxes, 16-bit Time Stamp Counter
• Two Multimedia Card Interfaces (MCI)
– SDCard/SDIO and MultiMedia
™
Card 3.31 Compliant
– Automatic Protocol Control and Fast Automatic Data Transfers with PDC
• Two Synchronous Serial Controllers (SSC)
– Independent Clock and Frame Sync Signals for Each Receiver and Transmitter
– I²S Analog Interface Support, Time Division Multiplex Support
– High-speed Continuous Data Stream Capabilities with 32-bit Data Transfer
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