
138
AT8xC5132
4173A–8051–08/02
I
DD,
I
DL
and I
PD
Test Conditions Figure 113. I
DD
Test Condition, Active Mode
Figure 114. I
DL
Test Condition, Idle Mode
Figure 115. I
PD
Test Condition, Power-Down Mode
X2
V
DD
lock Signal
RST
V
SS
TST
X1
P0
(NC)
IDD
All other pins are unconnected
V
DD
V
SS
V
DD
V
DD
X2
V
DD
Clock Signal
RST
V
SS
TST
X1
P0
(NC)
IDL
All other pins are unconnected
V
SS
V
DD
V
SS
V
DD
X2
V
DD
RST
V
SS
MCMD
X1
P0
(NC)
IPD
All other pins are unconnected
V
SS
V
DD
V
SS
V
DD
TST
MDAT
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