Rainbow-electronics AT89C5132 Manual do Utilizador descarregar pdf (Página 127)

127

AT8xC5132

4173A–8051–08/02

Slave Mode with Interrupt

Policy

Figure 102 shows the initialization phase and the transfer phase flows using the inter-

rupt policy.

The transfer format depends on the master controller.

Reading SPSTA at the beginning of the ISR is mandatory for clearing the SPIF flag.

Clear is effective when reading SPDAT.

Figure 104. Slave SPI Interrupt Policy Flows

Registers Table 114. SPCON Register

SPCON (S:C3h) – SPI Control Register

SPI Initialization

Interrupt Policy

Enable Interrupt

ESPI =1

SPI Interrupt

Service Routine

Select Slave Mode

MSTR = 0

Select Format

Program CPOL & CPHA

Enable SPI

SPEN = 1

Get Status

Read SPSTA

Prepare New Transfer

Write Data in SPDAT

Get Data Received

Read SPDAT

Prepare Transfer

Write Data in SPDAT

76543210

SPR2 SPEN SSDIS MSTR CPOL CPHA SPR1 SPR0

Bit

Number

Bit

Mnemonic Description

7SPR2

SPI Rate Bit 2

Refer to Table 113 for bit rate description.

6SPEN

SPI Enable Bit

Set to enable the SPI interface.

Clear to disable the SPI interface.

5SSDIS

Slave Select Input Disable Bit

Set to disable SS

in both master and slave modes. In slave mode this bit has no

effect if CPHA = 0.

Clear to enable SS

in both master and slave modes.

4MSTR

Master Mode Select

Set to select the master mode.

Clear to select the slave mode.

1 2 ... 122 123 124 125 126 127 128 129 130 131 132 ... 161 162

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