DC Electrical Characteristics
The following specifications apply for V
CC
e
5V
DC
and T
MIN
s
T
A
s
T
MAX
, unless otherwise specified.
Symbol Parameter Conditions MIn Typ Max Units
CONTROL INPUTS
[
Note: CLK IN is the input of a Schmitt trigger circuit and is therefore specified separately
]
V
IN
(1) Logical ‘‘1’’ Input Voltage V
CC
e
5.25 V
DC
2.0 15 V
DC
(Except CLK IN)
V
IN
(0) Logical ‘‘0’’ Input Voltage V
CC
e
4.75 V
DC
0.8 V
DC
(Except CLK IN)
I
IN
(1) Logical ‘‘1’’ Input Current V
IN
e
5V
DC
0.005 1 mA
DC
(All Inputs)
I
IN
(0) Logical ‘‘0’’ input Current V
IN
e
0V
DC
b
1
b
0.005 mA
DC
(All Inputs)
CLOCK IN
V
T
a
CLK IN Positive Going 2.7 3.1 3.5 V
DC
Threshold Voltage
V
T
b
CLK IN Negative Going 1.5 1.8 2.1 V
DC
Threshold Voltage
V
H
CLK IN Hysteresis 0.6 1.3 2.0 V
DC
(V
T
a
)
b
(V
T
b
)
OUTPUTS AND INTR
V
OUT
(0) Logical ‘‘0’’ Output Voltage I
OUT
e
1.6 mA, V
CC
e
4.75 V
DC
0.4 V
DC
V
OUT
(1) Logical ‘‘1’’ Output Voltage I
O
eb
360 mA, V
CC
e
4.75 V
DC
2.4 V
DC
I
O
eb
10 mA, V
CC
e
4.75 V
DC
4.5 V
DC
I
OUT
TRI-STATE Disabled Output V
OUT
e
0.4 V
DC
0.1
b
100 mA
DC
Leakage (All Data Buffers) V
OUT
e
5V
DC
0.1 3 mA
DC
I
SOURCE
V
OUT
Short to GND, T
A
e
25
§
C 4.5 6 mA
DC
I
SINK
V
OUT
Short to V
CC
,T
A
e
25
§
C 9.0 16 mA
DC
POWER SUPPLY
I
CC
Supply Current (Includes f
CLK
e
410 kHz,
Ladder Current) V
REF
/2
e
NC, T
A
e
25
§
C
and CS
e
1 2.5 5.0 mA
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating
the device beyond its specified operating conditions.
Note 2: All voltages are measured with respect to GND, unless otherwise specified. The separate A GND point should always be wired to the D GND.
Note 3: A zener diode exists, internally, from V
CC
to GND and has a typical breakdown voltage of 7 V
DC
.
Note 4: For V
IN
(
b
)
t
V
IN
(
a
) the digital output code will be all zeros. Two on-chip diodes are tied to each analog input (see Block Diagram) which will forward
conduct for analog input voltages one diode drop below ground or one diode drop greater than the V
CC
supply. Be careful, during testing at low V
CC
levels (4.5V),
as high level analog inputs (5V) can cause this input diode to conductÐespecially at elevated temperatures, and cause errors for analog inputs near fullscale. The
spec allows 50 mV forward bias of either diode. This means that as long as the analog V
IN
does not exceed the supply voltage by more than 50 mV, the output
code will be correct. To achieve an absolute 0 V
DC
to5V
DC
input voltage range will therefore require a minimum supply voltage of 4.950 V
DC
over temperature
variations, initial tolerance and loading.
Note 5: With an asynchronous start pulse, up to 8 clock periods may be required before the internal clock phases are proper to start the conversion process. The
start request is internally latched, see
Figure 1
.
Note 6: The CS
input is assumed to bracket the WR strobe input and therefore timing is dependent on the WR pulse width. An arbitrarily wide pulse width will hold
the converter in a reset mode and the start of conversion is initiated by the low to high transition of the WR
pulse (see Timing Diagrams).
Note 7: All typical values are for T
A
e
25
§
C.
Note 8: Accuracy is guaranteed at f
CLK
e
410 kHz. At higher clock frequencies accuracy can degrade.
Note 9: The V
REF/2
pin is the center point of a two resistor divider (each resistor is 2.4kX) connected from V
CC
to ground. Total ladder input resistance is the sum
of these two equal resistors.
Note 10: Human body model, 100 pF discharged through a 1.5 kX resistor.
3
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