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AT90SO4
6579A–SMS–29Jan10
Figure 1. AT90SO4 secureAVR Enhanced RISC Architecture
Instruction
Decoder
Program
Memory
Instruction
Register
Access
Control
General
Purpose
Registers
X
Y
Z
Status
Register
RAM
Data Memory
Interrupt
Unit
ISO 7816
I/O Port 0
Control
Lines
ALU
EEPROM
User Memory
OTP
PC
Secure
Control
VCC
GND
Access
Control
IN/OUT0
Data Bus
8-bit
RNG
16
16
16
8
88
DES
DPA Counter
measures
Reset
Circuit
RST
ISO 7816
Controller
CRC and
Checksum
Accelerator
Timer 1
Timer 0
ISO7816
I/O Port 1
SPI
Controller
SPI_MISO
SPICLK /
ISOCLK
SPI_MOSI
IN/OUT1 /
SS
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