Rainbow-electronics AT73C246 Manual do Utilizador

Features• AUDIO CODEC– 100dB Dynamic Range Stereo Audio DAC - 8 to 96 kHz sampling frequency– 96dB Dynamic Range Stereo Audio ADC - 8 to 96 kHz sampli

1011050A–PMAAC–07-Apr-10AT73C246

10011050A–PMAAC–07-Apr-10AT73C246Name: FRAME_CONTROLAccess: Read / WriteAddress: 0x14Note: 1. The Right-Justified mode is not provided for 12.0000 MH

10111050A–PMAAC–07-Apr-10AT73C246Name: MUTEAccess: Read / WriteAddress: 0x1576543210MUTEDACLMUTEDACRMUTEINL MUTEINR MUTEMICL MUTEMICR MUTEHPL MUTEHPR

10211050A–PMAAC–07-Apr-10AT73C246Name: MICLVOLAccess: Read / WriteAddress: 0x1676543210-- MICLVOLTable 13-37. MICLVOL (0x16) StructureBit Name Descri

10311050A–PMAAC–07-Apr-10AT73C246Name: MICRVOLAccess: Read / WriteAddress: 0x1776543210-- MICRVOLTable 13-39. MICRVOL (0x17) StructureBit Name Descri

10411050A–PMAAC–07-Apr-10AT73C246Name: INLVOLAccess: Read / WriteAddress: 0x1876543210INLBOTH INLVOLTable 13-41. INLVOL (0x18) StructureBit Name Desc

10511050A–PMAAC–07-Apr-10AT73C246Name: INRVOLAccess: Read / WriteAddress: 0x1976543210INRBOTH INRVOLTable 13-43. INRVOL (0x19) StructureBit Name Desc

10611050A–PMAAC–07-Apr-10AT73C246Name: HPLVOLAccess: Read / WriteAddress: 0x1A76543210HPLVOLTable 13-45. HPLVOL (0x1A) StructureBit Name Description

10711050A–PMAAC–07-Apr-10AT73C246Name: HPRVOLAccess: Read / WriteAddress: 0x1B76543210HPRVOLTable 13-47. HPRVOL (0x1B) StructureBit Name Description

10811050A–PMAAC–07-Apr-10AT73C246Name: HP_CONTROLAccess: Read / WriteAddress: 0x1C76543210-----HPDET_STLHPBOTHRHPBOTHTable 13-49. HP_CONTROL (0x1C) S

10911050A–PMAAC–07-Apr-10AT73C246Name: AUDIO_EFFECTSAccess: Read / WriteAddress: 0x1D765432103DFX_DEPTH ON3DFX SWAP_DAC SWAP_ADC MONO_DAC MONO_ADC ON

1111050A–PMAAC–07-Apr-10AT73C2466. Absolute Maximum RatingsNotes: 1. Refer to Power Dissipation Rating section2. According to specifications MIL-883-M

11011050A–PMAAC–07-Apr-10AT73C246Name: INPUT_CONTROLAccess: Read / Write. This register is modified by Audio Controller at audio path change.Address:

11111050A–PMAAC–07-Apr-10AT73C246Name: OUTPUT_CONTROLAccess: Read / WriteThis register is modified by Audio Controller at audio path change.Address:

11211050A–PMAAC–07-Apr-10AT73C246Name: INPUT_MIXERAccess: Read / WriteThis register is modified by Audio Controller at audio path change.Address: 0x2

11311050A–PMAAC–07-Apr-10AT73C246Name: SIDETONE_VOLAccess: Read / WriteAddress: 0x2176543210- - - SIDETONE_VOLTable 13-55. SIDETONE_VOL (0x21) Struct

11411050A–PMAAC–07-Apr-10AT73C246Name: EQUALIZERAccess: Read / WriteAddress: 0x2276543210---- EQ_SELTable 13-57. EQUALIZER (0x22) StructureBit Name D

11511050A–PMAAC–07-Apr-10AT73C246Name: ADC_CTRLAccess: Read / WriteAddress: 0x3076543210ON_ADC ON_BUF - - - TSTable 13-59. ADC_CTRL (0x30) StructureB

11611050A–PMAAC–07-Apr-10AT73C246Name: ADC_MUX_1Access: Read / WriteAddress: 0x3176543210- VIN - VDD4 VDD3 VDD2 VDD1 VDD0Table 13-61. ADC_MUX1 (0x31)

11711050A–PMAAC–07-Apr-10AT73C246Name: ADC_MUX_2Access: Read / WriteAddress: 0x3276543210----ANA3ANA2ANA1ANA0Table 13-62. ADC_MUX2 (0x32) StructureBi

11811050A–PMAAC–07-Apr-10AT73C246Name: ADC_ANA0_MSBAccess: Read OnlyAddress: 0x33Name: ADC_ANA0_LSBAccess: Read OnlyAddress: 0x3476543210ADC<9:2>

11911050A–PMAAC–07-Apr-10AT73C246Name: ADC_ANA1_MSBAccess: Read OnlyAddress: 0x35Name: ADC_ANA1_LSBAccess: Read OnlyAddress: 0x3676543210ADC<9:2>

1211050A–PMAAC–07-Apr-10AT73C2469. PMU Electrical Characteristics9.1 Current Consumption Versus Modes9.2 Supply Monitor ThresholdsThe following table

12011050A–PMAAC–07-Apr-10AT73C246Name: ADC_ANA2_MSBAccess: Read OnlyAddress: 0x37Name: ADC_ANA2_LSBAccess: Read OnlyAddress: 0x3876543210ADC<9:2>

12111050A–PMAAC–07-Apr-10AT73C246Name: ADC_ANA3_MSBAccess: Read OnlyAddress: 0x39Name: ADC_ANA3_LSBAccess: Read OnlyAddress: 0x3A76543210ADC<9:2>

12211050A–PMAAC–07-Apr-10AT73C246Name: ADC_VDD0_MSBAccess: Read OnlyAddress: 0x3BName: ADC_VDD0_LSBAccess: Read OnlyAddress: 0x3C76543210ADC<9:2>

12311050A–PMAAC–07-Apr-10AT73C246Name: ADC_VDD1_MSBAccess: Read OnlyAddress: 0x3DName: ADC_VDD1_LSBAccess: Read OnlyAddress: 0x3E76543210ADC<9:2>

12411050A–PMAAC–07-Apr-10AT73C246Name: ADC_VDD2_MSBAccess: Read OnlyAddress: 0x3FName: ADC_VDD2_LSBAccess: Read OnlyAddress: 0x4076543210ADC<9:2>

12511050A–PMAAC–07-Apr-10AT73C246Name: ADC_VDD3_MSBAccess: Read OnlyAddress: 0x41Name: ADC_VDD3_LSBAccess: Read OnlyAddress: 0x4276543210ADC<9:2>

12611050A–PMAAC–07-Apr-10AT73C246Name: ADC_VDD4_MSBAccess: Read OnlyAddress: 0x43Name: ADC_VDD4_LSBAccess: Read OnlyAddress: 0x4476543210ADC<9:2>

12711050A–PMAAC–07-Apr-10AT73C246Name: ADC_VIN_MSBAccess: Read OnlyAddress: 0x47Name: ADC_VIN_LSBAccess: Read OnlyAddress: 0x4876543210ADC<9:2>T

12811050A–PMAAC–07-Apr-10AT73C246Name: ADC_ANA_LSBAccess: Read OnlyAddress: 0x49Name: RTC_CTRLAccess: Read / WriteAddress: 0x5076543210ADC_ANA3<1:

12911050A–PMAAC–07-Apr-10AT73C246Name: RTC_ADDRAccess: Read / WriteAddress: 0x51Name: RTC_DATA0Access: Read / WriteAddress: 0x5276543210RTC_ADDRTabl

1311050A–PMAAC–07-Apr-10AT73C2469.3 Digital I/Os DC CharacteristicsNotes: 1. VPAD referred pins ITB, RSTB: open drain outputs. Only VOL and IO paramet

13011050A–PMAAC–07-Apr-10AT73C246Name: RTC_DATA1Access: Read / WriteAddress: 0x53Name: RTC_DATA2Access: Read / WriteAddress: 0x54Name: RTC_DATA3Acce

13111050A–PMAAC–07-Apr-10AT73C246Name: BACKUP_CTRLAccess: Read / WriteAddress: 0x56Name: VERSIONAccess: ReadAddress: 0x7F76543210----OSC_UPDTOSC_ENOS

13211050A–PMAAC–07-Apr-10AT73C24614. PMU and Audio Soft Control: Quick Start14.1 RTC Examples14.1.1 RTC Oscillator POWER-ON // Set OSC_EN = 1 and OSC_

13311050A–PMAAC–07-Apr-10AT73C246TWI_WRITE DATA2 @RTC_DATA2TWI_WRITE DATA3 @RTC_DATA3// Set RTC_WRITE = 1 (write) and RTC_SEL = 1TWI_WRITE 0x06 @ RTC_

13411050A–PMAAC–07-Apr-10AT73C246// Write Time @RTC_TIMR (RTC_ADDR = 0x08) (08h 49min 59s)WRITE_RTC 0x00084959 @RTC_TIMR// Start RTC @RTC_CR (RTC_ADDR

13511050A–PMAAC–07-Apr-10AT73C246// Wait (3.tau) = 300ms with 1uF before standby release. (VMID will be // discharged only when ENAC = 0.)// From this

13611050A–PMAAC–07-Apr-10AT73C246// Start LDO4 @3.3VTWI_WRITE 0x8C @ VDD4_CTRL// Digital Audio Interface configuration// Master clock = 12.288MHz, Mas

13711050A–PMAAC–07-Apr-10AT73C246// account. TWI_WRITE 0x3F @ AUDIO_CONTROLTWI_WRITE 0x2F @ AUDIO_CONTROL// STANDBY release. The codec softly starts.T

13811050A–PMAAC–07-Apr-10AT73C246

13911050A–PMAAC–07-Apr-10AT73C24615. Typical Performance Characteristics15.1 PMU: Power Supply SequencesFigure 15-1. Powerdown State to Run State Supp

1411050A–PMAAC–07-Apr-10AT73C2469.4 DCDC0 and DCDC1Unless otherwise specified: External components L=2.2μH, COUT=22μF and CIN=10μF. VIN{0,1} > VDD{

14011050A–PMAAC–07-Apr-10AT73C246Figure 15-3. Detailed Supplies Start-UpFigure 15-4. Detailed Supplies ShutdownDetailed Supplies Start-UpSEQUENCE ADet

14111050A–PMAAC–07-Apr-10AT73C246Figure 15-5. Run State to Standby StateFigure 15-6. Standby To Run StateRun To Standby State (default setting)SEQUENC

14211050A–PMAAC–07-Apr-10AT73C24615.2 DCDC0 and DCDC1Unless otherwise noted, the reported measurement were performed at room temperature. External com

14311050A–PMAAC–07-Apr-10AT73C246Figure 15-8. DCDC0 Ripple and Efficency PerformanceDCDC0 - VOUT = 1.8VEfficiency in PFM and PWM modesDCDC0 - VIN = 5.

14411050A–PMAAC–07-Apr-10AT73C246Figure 15-9. DCDC1Transient Load Regulation PerformanceDCDC0 - VIN = 3.3V - VOUT = 1.2VLoad Step 0 To 600mA / 1us DCD

14511050A–PMAAC–07-Apr-10AT73C246Figure 15-10. DCDC0 Ripple and Efficiency PerformanceDCDC1 - VOUT = 1.2VEfficiency in PFM and PWM modesDCDC1 - VIN =

14611050A–PMAAC–07-Apr-10AT73C24615.3 LDO2Unless otherwise noted, the reported measurement were performed at room temperature. External components are

14711050A–PMAAC–07-Apr-10AT73C24615.4 LDO3Unless otherwise noted, the reported measurement were performed at room temperature. External components are

14811050A–PMAAC–07-Apr-10AT73C24615.5 AUDIOUnless otherwise noted, the reported measurement were performed at room temperature with AVDD = 3.3V suppli

14911050A–PMAAC–07-Apr-10AT73C246Figure 15-14. DAC Playback WaveformsDAC playback ( Path 1) - Load 10k0 dBFs / 1kHz Input - Fs = 48kHz - 32kpts FFTDA

1511050A–PMAAC–07-Apr-10AT73C246Notes: 1. Current consumption without load. One DCDC converter ON, the other one OFF.2. Default output voltage are set

15011050A–PMAAC–07-Apr-10AT73C246Figure 15-15. Line Record Waveforms Line Record (path 7)-1 dBV / 1kHz Input - Fs = 48kHz - 32kpts FFTLine Record (pa

15111050A–PMAAC–07-Apr-10AT73C246Figure 15-16. Line Bypass WaveformsLine Bypass (path 5)0 dBV / 1kHz Input - 10k load - 16kpts FFTLine Bypass (path 5

15211050A–PMAAC–07-Apr-10AT73C246

15311050A–PMAAC–07-Apr-10AT73C24616. Package InformationFigure 16-1. Mechanical Package Drawing for 64-lead Quad Flat No Lead Package

15411050A–PMAAC–07-Apr-10AT73C24617. Ordering InformationNotes: 1. See “VERSION” (0x7F) register definition.2. See “Power Manager State Description” o

15511050A–PMAAC–07-Apr-10AT73C24618. Revision HistoryTable 18-1. Revision HistoryDoc. Rev Date Comments Change Request Ref. 11050A 07-Apr-10 First is

15611050A–PMAAC–07-Apr-10AT73C246

i11050A–PMAAC–07-Apr-10AT73C2461 Description ... 22 Block

ii11050A–PMAAC–07-Apr-10AT73C24612 Audio Codec Functional Description ... 5512.1Description ...

Headquarters InternationalAtmel Corporation2325 Orchard ParkwaySan Jose, CA 95131USATel: 1(408) 441-0311Fax: 1(408) 487-2600Atmel AsiaRoom 1219Chinach

1611050A–PMAAC–07-Apr-10AT73C2469.5 LDO2Unless otherwise specified: External components COUT=10µF, CIN=10μF, TJ = [-40°C ; +125°C].Notes: 1. Current c

1711050A–PMAAC–07-Apr-10AT73C2469.6 LDO3Unless otherwise specified: External components COUT=10µF, CIN=10μF, TJ = [-40°C ; +125°C].Notes: 1. Current c

1811050A–PMAAC–07-Apr-10AT73C2469.7 LDO4Unless otherwise specified: External components COUT=10µF, CIN=10μF, TJ = [-40°C ; +125°C].Notes: 1. Current c

1911050A–PMAAC–07-Apr-10AT73C2469.8 LDO5Unless otherwise specified: External components COUT=2.2µF, CIN=10μF, TJ = [-40°C ; +125°C].Note: 1. Current c

211050A–PMAAC–07-Apr-10AT73C2461. DescriptionThe AT73C246 is an integrated high performance Power Management and Audio IC. It is specif-ically designe

2011050A–PMAAC–07-Apr-10AT73C2469.9 Measurement Bridge and 10-bit ADC Notes: 1. The 10-bit ADC is supplied from the regulated VDDC voltage (1.8V) whic

2111050A–PMAAC–07-Apr-10AT73C2469.10 RTC Crystal OscillatorNote: 1. Current consumption in VBACKUP with crystal. In case of crystal not present on-boa

2211050A–PMAAC–07-Apr-10AT73C24610. Audio Codec Electrical CharacteristicsUnless otherwise specified: AVDD = 3.3V, TA = 25C, MCLK = 12.288MHz, FS = 48

2311050A–PMAAC–07-Apr-10AT73C246DR Dynamic Range(3)AVDD = 3.3V 85 96 - dBAVDD = 2.7V 82 93 - dBTHD Total Harmonic Distortion -1dBFS digital output - -

2411050A–PMAAC–07-Apr-10AT73C246Notes: 1. Full Scale: A linear extrapolation to 0dBFS of the measured level at -10dBFS.2. Signal-to-Noise Ratio: The r

2511050A–PMAAC–07-Apr-10AT73C24611. PMU Functional Description11.1 Power Manager State DiagramFigure 11-1. AT73C246 Power Manager Functional State Dia

2611050A–PMAAC–07-Apr-10AT73C24611.2 PMU Startup and Shutdown State DiagramFigure 11-2. AT73C246 Start-up and Shutdown State DiagramThe start-up of th

2711050A–PMAAC–07-Apr-10AT73C246(VDDC = 1.8V) is started. During this PMU reset, the ‘LED’ pin is driven to VINSYS (LED is OFF).• When VDDC is ready a

2811050A–PMAAC–07-Apr-10AT73C24611.3.6 WAKEUP EVENTSWAKEUP EVENTS are validated if one of the listed condition is true:• WAKEUP0 pin goes from low to

2911050A–PMAAC–07-Apr-10AT73C24611.4 Power Manager State DescriptionAT73C246 ICs are available with 2 factory programmed power sequences. The followin

311050A–PMAAC–07-Apr-10AT73C2462. Block DiagramFigure 2-1. AT73C246 functional block diagramLDO43.3V(CODEC)AUDIOCODECDIGITALCOREVIN4VIN0SW0VFB0GND0BUC

3011050A–PMAAC–07-Apr-10AT73C246Figure 11-3. AT73C246 - RUN to POWERDOWN state Supplies Shutdown timing diagram.Note: 1. VDDx activity during RUN stat

3111050A–PMAAC–07-Apr-10AT73C246When the POWERDOWN state is reached from the STANDBY state, the CPU power suppliesare switched off sequentially as des

3211050A–PMAAC–07-Apr-10AT73C246When RUN state is reached from the POWERDOWN state, the power supplies are sequentiallystarted-up according to the Fig

3311050A–PMAAC–07-Apr-10AT73C246When RUN state is reached from the STANDBY state, the power supplies are sequentiallystarted-up according to the Figur

3411050A–PMAAC–07-Apr-10AT73C246Figure 11-7. AT73C246 - RUN to STANDBY state Supplies Shutdown timing diagram.Note: 1. VDDx activity during STANDBY st

3511050A–PMAAC–07-Apr-10AT73C246Figure 11-8. AT73C246 - HRST state Supplies Shutdown timing diagram.Note: 1. VDDx activity during RUN state is set by

3611050A–PMAAC–07-Apr-10AT73C24611.5 DCDC0 and DCDC1 Functional DescriptionDCDC0 and DCDC1 are 2 identical high performance synchronous step-down (buc

3711050A–PMAAC–07-Apr-10AT73C24611.6 LDO2 Functional DescriptionLDO2 is a linear voltage regulator intended to supply CPU core voltages in the range 0

3811050A–PMAAC–07-Apr-10AT73C246At power up, LDO3 an LDO4 default output voltages are both 3.3V. For different default outputvoltages, please contact

3911050A–PMAAC–07-Apr-10AT73C246Figure 11-9. Measurement Bridge and 10-bit ADC Block Diagram.VREFPADCVINSYSVDD0VDD1VDD2VDD3VDD4ANA0ANA1ANA2ANA3ADC_ANA

411050A–PMAAC–07-Apr-10AT73C2463. Package and Pinout Figure 3-1. AT73C246 QFN64 package pinout - Top view11617 3233484964VBACKUPLEDANA0ANA1ANA2ANA3VIN

4011050A–PMAAC–07-Apr-10AT73C24611.10 Real Time Clock (RTC) User Interface Figure 11-10. RTC Block DiagramNote: 1. Values in the Version Register vary

4111050A–PMAAC–07-Apr-10AT73C24611.10.1 RTC Register Read/Write OperationFigure 11-11. RTC Read OperationFigure 11-12. RTC Write OperationRTC_ENRTC_SE

4211050A–PMAAC–07-Apr-10AT73C24611.10.2 RTC Control RegisterName: RTC_CRAccess: Read-writeAddress: 0x00• UPDTIM: Update Request Time Register0 = No ef

4311050A–PMAAC–07-Apr-10AT73C24611.10.3 RTC Mode RegisterName: RTC_MRAccess: Read-writeAddress: 0x04• HRMOD: 12-/24-hour Mode0 = 24-hour mode is selec

4411050A–PMAAC–07-Apr-10AT73C24611.10.4 RTC Time RegisterName: RTC_TIMRAccess: Read-writeAddress: 0x08 • SEC: Current SecondThe range that can be set

4511050A–PMAAC–07-Apr-10AT73C24611.10.5 RTC Calendar RegisterName: RTC_CALRAccess: Read-writeAddress: 0x0C•CENT: Current CenturyThe range that can be

4611050A–PMAAC–07-Apr-10AT73C24611.10.6 RTC Time Alarm RegisterName: RTC_TIMALRAccess: Read-writeAddress: 0x10 • SEC: Second AlarmThis field is the al

4711050A–PMAAC–07-Apr-10AT73C24611.10.7 RTC Calendar Alarm RegisterName: RTC_CALALRAccess: Read-writeAddress: 0x14 • MONTH: Month AlarmThis field is t

4811050A–PMAAC–07-Apr-10AT73C24611.10.8 RTC Status RegisterName: RTC_SRAccess: Read-onlyAddress: 0x18 • ACKUPD: Acknowledge for Update0 = Time and cal

4911050A–PMAAC–07-Apr-10AT73C24611.10.9 RTC Status Clear Command RegisterName: RTC_SCCRAccess: Write-onlyAddress: 0x1C • ACKCLR: Acknowledge Clear0 =

511050A–PMAAC–07-Apr-10AT73C2464. Pin DescriptionTable 4-1. Pin DescriptionPin Name I/O Pin Number Type FunctionVBACKUP Output 1 Analog RTC supplyLED

5011050A–PMAAC–07-Apr-10AT73C24611.10.10 RTC Interrupt Enable RegisterName: RTC_IERAccess: Write-onlyAddress: 0x20 • ACKEN: Acknowledge Update Interru

5111050A–PMAAC–07-Apr-10AT73C24611.10.11 RTC Interrupt Disable RegisterName: RTC_IDRAccess: Write-onlyAddress: 0x24 • ACKDIS: Acknowledge Update Inter

5211050A–PMAAC–07-Apr-10AT73C24611.10.12 RTC Interrupt Mask RegisterName: RTC_IMRAccess: Read-onlyAddress: 0x28 • ACK: Acknowledge Update Interrupt Ma

5311050A–PMAAC–07-Apr-10AT73C24611.10.13 RTC Valid Entry RegisterName: RTC_VERAccess: Read-onlyAddress: 0x2C • NVTIM: Non-valid Time0 = No invalid dat

5411050A–PMAAC–07-Apr-10AT73C24611.10.14 RTC Version registerName: RTC_VERSIONAccess: Read-onlyAddress: 0xFC • VERSIONReserved. Value subject to chang

5511050A–PMAAC–07-Apr-10AT73C24612. Audio Codec Functional Description 12.1 DescriptionAT73C246 features a high quality, low power stereo audio codec

5611050A–PMAAC–07-Apr-10AT73C24612.3 Audio Codec ControlsFigure 12-2. Audio Codec ControlsBCLKINVENASRSTDBYENACLINBOTHRINBOTHDAIMODEMCLKSELSELFSRHSBOT

5711050A–PMAAC–07-Apr-10AT73C24612.4 Audio ControllerThe audio controller sequences the power-up and power-down of the audio codec sub-functions(Mic.a

5811050A–PMAAC–07-Apr-10AT73C24612.4.1 Audio Codec General Recommendations12.4.1.1 VMID•VMID is the common mode voltage of the audio codec analog core

5911050A–PMAAC–07-Apr-10AT73C246Figure 12-4. AC / DC Coupled Load Management Schematic ViewFigure 12-5. Audio Codec Typical Startup and Shutdown Wavef

611050A–PMAAC–07-Apr-10AT73C246MICLN Input 31 Analog Audio negative microphone input leftMICRN Input 32 Analog Audio negative microphone input rightMI

6011050A–PMAAC–07-Apr-10AT73C246500ms timeout. Contrary to the first point, which has no timeout, the audio power-off time limit is here fixed to 500m

6111050A–PMAAC–07-Apr-10AT73C246master clock must be running to properly shutdown the codec. This time linearly varies withASR_TIME value. See Table 1

6211050A–PMAAC–07-Apr-10AT73C24612.4.2.2 Pause Management With STANDBY BitTo pause the audio codec activity and reduce power consumption to few hundre

6311050A–PMAAC–07-Apr-10AT73C246• INPUT_CONTROL (0x1E)• OUTPUT_CONTROL (0x1F)• INPUT_MIXER (0x20)Like in the automatic path configuration, the audio c

6411050A–PMAAC–07-Apr-10AT73C246• Current consumptions don’t account for load consumption and are measured in AVDD pin and VINSYS pin.Table 12-2. Audi

6511050A–PMAAC–07-Apr-10AT73C24610111DAC Playback + Line Bypassand Line RecordDigital + Line IN - Headphone OUTLine IN - Digital OUT3.80 8.00 mA11000D

6611050A–PMAAC–07-Apr-10AT73C24612.6 Digital Audio Interface12.6.1 General DescriptionAT73C246 features a 16 to 24-bit multi-mode master / slave I2S p

6711050A–PMAAC–07-Apr-10AT73C24612.6.3 Data Transfer: Left Justified ModeFigure 12-8. N-bit Left Justified Mode (FS = 44.1KHz - MCLK = 256 x FS)12.6.4

6811050A–PMAAC–07-Apr-10AT73C24612.6.5 Timing SpecificationsFigure 12-10. Timing Diagram of data interface (I²S Mode)12.7 Digital Filters Transfer Fun

6911050A–PMAAC–07-Apr-10AT73C246Figure 12-12. DAC Type 1 Frequency ResponseFigure 12-13. DAC Type 2 Frequency ResponseFigure 12-14. DAC Type 3 Frequen

711050A–PMAAC–07-Apr-10AT73C246XIN Input 63 Analog RTC crystal oscillator inputXOUT Output 64 Analog RTC crystal oscillator outputDGND Ground 65 Analo

7011050A–PMAAC–07-Apr-10AT73C246Figure 12-15. DAC Type 4 Frequency Response12.7.2 ADC Frequency ResponseThe following diagrams are referred to FS = 1

7111050A–PMAAC–07-Apr-10AT73C246Figure 12-18. ADC Type 2 Frequency ResponseFigure 12-19. ADC Type 3 Frequency ResponseFigure 12-20. ADC Type 4 Frequen

7211050A–PMAAC–07-Apr-10AT73C24612.7.3 De-Emphasis Filter Frequency Response12.7.3.1 De-Emphasis Filter: Frequency Response & Error (FS = 32kHz)Fi

7311050A–PMAAC–07-Apr-10AT73C24612.7.4 Equalizer Frequency ResponseThe following figures show the frequency response of the equalizer function impleme

7411050A–PMAAC–07-Apr-10AT73C246Figure 12-26. Treble Filters Response12.8 Analog Audio Interfaces12.8.1 Microphone InputsThe following figures show re

7511050A–PMAAC–07-Apr-10AT73C246Figure 12-27. Mono - Single Ended and Differential Microphone ApplicationsFigure 12-28. Stereo - Single Ended and Diff

7611050A–PMAAC–07-Apr-10AT73C24612.8.2 Aux / Line InputsFigure 12-30. Aux and Line Input Application Circuits12.8.3 Line / Headphone OutputsFigure 12-

7711050A–PMAAC–07-Apr-10AT73C24613. Two Wire Interface and Control Registers13.1 Two-wire Interface (TWI) ProtocolThe two-wire interface interconnects

7811050A–PMAAC–07-Apr-10AT73C246For a read operation a repeated Start condition needs to be generated followed by a read on thedevice.Figure 13-3. TWD

7911050A–PMAAC–07-Apr-10AT73C24613.2 PMU Register Tables13.2.1 Register MappingTable 13-1. Register MappingAddrName 765432100x00 PMU_MODES - - - - - S

811050A–PMAAC–07-Apr-10AT73C2465. Application Block DiagramFigure 5-1. AT73C246 Application Block DiagramLDO43.3V(CODEC)VINC41AUDIOCODECDIGITALCOREVIN

8011050A–PMAAC–07-Apr-10AT73C2460x34 ADC_ANA0_LSB - - - - - - ADC<1:0>0x35 ADC_ANA1_MSB ADC<9:2>0x36 ADC_ANA1_LSB - - - - - - ADC<1:0&g

8111050A–PMAAC–07-Apr-10AT73C24613.2.2 PMU ControlName: PMU_MODESAccess: Read / WriteAddress: 0x00Notes: 1. Please refer to Section 11. “PMU Function

8211050A–PMAAC–07-Apr-10AT73C246Name: PMU_WAKEUP_EVENTSAccess: Read / WriteAddress: 0x01Note: Please refer to Section 11. “PMU Functional Description

8311050A–PMAAC–07-Apr-10AT73C246Name: PMU_WAKEUP_TRIGAccess: Read OnlyAddress: 0x02Note: Please refer to Section 11. “PMU Functional Description” on p

8411050A–PMAAC–07-Apr-10AT73C246Name: PMU_STANDBY_SUPPLIESAccess: Read / WriteAddress: 0x0376543210- - LP_VDD1 LP_VDD0 VDD3 VDD2 VDD1 VDD0Table 13-5.

8511050A–PMAAC–07-Apr-10AT73C246Name: PMU_SUPPLY_CTRLAccess: Read / WriteAddress: 0x0476543210- - IN_PHASE DVS_VDD4 DVS_VDD3 DVS_VDD2 DVS_VDD1 DVS_VD

8611050A–PMAAC–07-Apr-10AT73C246Name: PMU_RST_LVLAccess: Read / WriteAddress: 0x0576543210RST_VDD3 RST_VDD2 RST_VDD1 RST_VDD0Table 13-7. PMU_RST_LVL

8711050A–PMAAC–07-Apr-10AT73C246Name: VDD0_CTRLAccess: Read / WriteAddress: 0x0676543210ON_VDD0 LPMODE VDD0_SELTable 13-9. VDD0_CTRL (0x06) Structure

8811050A–PMAAC–07-Apr-10AT73C246Name: VDD1_CTRLAccess: Read / WriteAddress: 0x0776543210ON_VDD1 LPMODE VDD1_SELTable 13-11. VDD1_CTRL (0x07) Structur

8911050A–PMAAC–07-Apr-10AT73C246Name: VDD2_CTRLAccess: Read / WriteAddress: 0x0876543210ON_VDD2 - - VDD2_SELTable 13-13. VDD2_CTRL (0x08) StructureBi

911050A–PMAAC–07-Apr-10AT73C246Table 5-1. Typical Application Components DesignSchematic Reference Value DescriptionR1, R18, R19, R22, R23 2kΩ 5% / 0.

9011050A–PMAAC–07-Apr-10AT73C246Name: VDD3_CTRLAccess: Read / WriteAddress: 0x0976543210ON_VDD3 - - VDD3_SELTable 13-15. VDD3_CTRL (0x09) StructureBi

9111050A–PMAAC–07-Apr-10AT73C246Name: VDD4_CTRLAccess: Read / WriteAddress: 0x0A76543210ON_VDD4 - - VDD4_SELTable 13-17. VDD4_CTRL (0x0A) StructureBi

9211050A–PMAAC–07-Apr-10AT73C246Name: PMU_LEDAccess: Read / WriteAddress: 0x0BNote: In case of TON_LED = 175ms, PERIOD_LED=5s and BLINK=1 selection,

9311050A–PMAAC–07-Apr-10AT73C246Name: PMU_MASKAccess: Read / WriteAddress: 0x0CName: PMU_ITAccess: Read OnlyAddress: 0x0D76543210------RTC_ALARMRTC_I

9411050A–PMAAC–07-Apr-10AT73C246Name: PMU_WAKEUP_SUPPLIESAccess: Read / WriteAddress: 0x0E76543210----VDD0_WUPVDD1_WUPVDD2_WUPVDD3_WUPTable 13-23. PM

9511050A–PMAAC–07-Apr-10AT73C246Name: AUTOSTARTAccess: Read / WriteAddress: 0x1076543210- ENAC STANDBY PATH_SELTable 13-24. AUTOSTART (0x10) Structur

9611050A–PMAAC–07-Apr-10AT73C24610011DAC Playback andAux RecordDigital IN - Headphone OUTAux IN - Digital OUT10100DAC Playback andLine RecordDigital I

9711050A–PMAAC–07-Apr-10AT73C246Name: AUDIO_CONTROLAccess: Read / WriteAddress: 0x1176543210- BCLKINV DCBLOCK ENCONFCUST_CONFENASR ASR_TIMETable 13-2

9811050A–PMAAC–07-Apr-10AT73C246Name: MIC_CONTROLAccess: Read / WriteAddress: 0x1276543210- - MICLDIFF MICRDIFF MICDET ONMICBIAS MICDET_STTable 13-28

9911050A–PMAAC–07-Apr-10AT73C246Name: DAI_CONTROLAccess: Read / WriteAddress: 0x13Note: 1. The MASTER mode is not provided for 12.0000 MHz clock case