
30
11050A–PMAAC–07-Apr-10
AT73C246
Figure 11-3. AT73C246 - RUN to POWERDOWN state Supplies Shutdown timing diagram.
Note: 1. VDDx activity during RUN state is set by Bit7 of register VDDx_CTRL.
Table 11-2. RUN to POWERDOWN state timing table
Symbol Parameter Comments Min Typ Max Units
T
PWRDOWN
POWERDOWN Event detection
time
58 62 66 µs
T
OFF_AUDIO
Audio CODEC Shutdown Time
Audio CODEC is OFF or Power Fail
Occurs
58 62 66 µs
Audio CODEC is ON 486 512 538 ms
T
OFF_VDDx
VDDx SHUTDOWN Time
VDDx is OFF in RUN state
(1)
58 62 66 µs
VDDx is ON in RUN state
(1)
4.8 5.2 5.4 ms
RUN
STATE
SUPPLIES SHUTDOWN
POWEROFF
EVENT
POWERDOWN
STATE
T
PWRDOWN
T
OFF_AUDIO
T
OFF_VDD3
V
DD3
(3.3V)
V
DD1
(1.2V)
V
DD2
(1V)
3.3V
1.2V
1V
RSTB
V
DD0
(1.85V)
T
OFF_VDD1
T
OFF_VDD0
T
OFF_VDD2
V
DD4
(CODEC)
T
OFF_VDD4
1.85V
RUN
STATE
SUPPLIES SHUTDOWN
POWEROFF
EVENT
POWERDOWN
STATE
T
PWRDOWN
T
OFF_AUDIO
T
OFF_VDD2
V
DD2
(1V)
V
DD1
(1.2V)
V
DD3
(3.3V)
1V
1.2V
3.3V
RSTB
V
DD0
(1.85V)
T
OFF_VDD1
T
OFF_VDD0
T
OFF_VDD3
V
DD4
(CODEC)
T
OFF_VDD4
1.85V
SEQUENCE A SEQUENCE B
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