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Functional Description (Continued)

The remaining four LSBs may now be determined using the

same sixteen comparators that were used for the first flash

conversion. The MSB Ladder tap voltage just below the in-

put voltage (as determined by the first flash) is subtracted

from the input voltage and compared with the tap points on

the sixteen LSB Ladder resistors. The result of this second

flash conversion is then decoded, and the full 10-bit result is

latched.

Note that the sixteen comparators used in the first flash

conversion are reused for the second flash. Thus, the half-

flash conversion techniques used in the ADC1061 needs

only a small fraction of the number of comparators that

would be required for a traditional flash converter, and far

fewer than would be used in a conventional half-flash ap-

proach. This allows the ADC1061 to perform high-speed

conversions without excessive power drain.

Applications Information

1.0 Modes of Operation

The ADC1061 has two basic digital interface modes. These

are illustrated in

Figure 1

and

Figure 2

MODE 1

In this mode, the S

/H pin controls the start of conversion.

/H is pulled low for a minimum of 250 ns. This causes the

comparators in the ‘‘coarse’’ flash converter to become ac-

tive. When S

/H goes high, the result of the coarse conver-

sion is latched and the ‘‘fine’’ conversion begins. After ap-

proximately 1.2 ms (1.8 ms maximum), INT

goes low, indicat-

ing that the conversion results are latched and can be read

by pulling RD

low. Note that CS must be low to enable S/H

or RD

.CSis internally ‘‘ANDed’’ with the sample and read

control signals; the input voltage is sampled when CS

and

/H are low, and is read when CS and RD are low.

MODE 2

In Mode 2, also called ‘‘RD mode’’, the S

/H and RD pins

are tied together. A conversion is initiated by pulling both

pins low. The ADC1061 samples the input voltage and

causes the coarse comparators to become active. An inter-

nal timer then terminates the coarse conversion and begins

the fine conversion.

About 1.8 ms (2.4 ms maximum) after S

/H and RD are

pulled low, INT

goes low, indicating that the conversion is

complete. Approximately 20 ns later the data appearing on

the TRI-STATE output pins will be valid. Note that data will

appear on these pins throughout the conversion, but will be

valid only after INT

goes low.

TL/H/10559–14

FIGURE 4. Typical connection. Note the multiple bypass capacitors on the reference

and power supply pins. If V

REF

is not grounded, it should also be bypassed to

ground using multiple capacitors (see 5.0 ‘‘Power Supply Considerations’’).

1 2 3 4 5 6 7 8 9 10 11 12

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