
6
4891CS–GPS–01/06
ATR0622 [Preliminary]
P14 1 I/O Configurable (PD) NAADET1 “0”
P15 17 I/O PD ANTON
P16 6 I/O Configurable (PU) NEEPROM SIGHI1 NWD_OVF
P17 2 I/O Configurable (PD) GPSMODE5 SCK1 SCK1
P18 45 I/O Configurable (PU) TXD1 TXD1 “0”
P19 53 I/O Configurable (PU) GPSMODE6 SIGLO1 “0”
P20 4 I/O Configurable (PD) TIMEPULSE SCK2 SCK2 TIMEPULSE
P21 52 I/O Configurable (PU) TXD2 TXD2 “0”
P22 30 I/O PU RXD2 RXD2
P23 3 I/O Configurable (PU) GPSMODE7 SCK SCK MCLK_OUT
P24 5 I/O Configurable (PU) GPSMODE8 MOSI MOSI “0”
P25 55 I/O Configurable (PD) NAADET0 MISO MISO “0”
P26 44 I/O Configurable (PU) GPSMODE10 NSS NPCS0 “0”
P27 54 I/O Configurable (PU) GPSMODE11 NPCS1
P29 50 I/O Configurable (PU) GPSMODE12 NPCS3
P30 16 I/O PD AGCOUT0 AGCOUT0 “0”
P31 31 I/O PU RXD1 RXD1
RF_ON 15 OUT PD
SIGHI0 38 IN
SIGLO0 39 IN
TCK 9 IN PU
TDI 10 IN PU
TDO 11 OUT
TMS 12 IN PU
USB_DM 34 I/O
USB_DP 35 I/O
VBAT 22 IN
VBAT18
(3)
23 OUT
VDD18 7, 14 IN
VDD18 18, 36 IN
VDD18 51 IN
VDDIO
(4)
43, 56 IN
VDD_USB
(5)
33 IN
XT_IN 28 IN
XT_OUT 27 OUT
NC
(6)
42
Table 3-1. ATR0622 Pinout (Continued)
Pin Name QFN56
Pin
Type
Pull Resistor
(Reset Value)
(1)
Firmware Label
PIO Bank A PIO Bank B
IOIO
Notes: 1. PD = internal pull-down resistor, PU = internal pull-up resistor, OH = switched to Output High at reset
2. Ground plane
3. VBAT18 represent the internal power supply of the backup power domain, see section “Power Supply” on page 17.
4. VDDIO is the supply voltage for the following GPIO-pins: P1, P2, P8, P12, P14, P16, P17, P18, P19, P20, P21, P23, P24,
P25, P26, P27 and P29, see section “Power Supply” on page 17.
5. VDD_USB is the supply voltage for following the USB-pins: USB_DM and USB_DP, see section “Power Supply” on page
17. For operation of the USB interface, supply of 3.0V to 3.6V is required.
6. This pin is not connected
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