Rainbow-electronics MAX7315 Manual do Utilizador descarregar pdf (Página 15)

output port registers, and using the software or hard-

ware controls to flip between the patterns.

If the blink phase 1 register is written with 0xFF, then

the BLINK input can be used as a hardware disable to,

for example, instantly turn off an LED pattern pro-

grammed into the blink phase 0 register. This tech-

nique can be further extended by driving the BLINK

input with a PWM signal to modulate the LED current to

provide fading effects.

The blink mode is enabled by setting the blink enable

flag E in the configuration register (Table 4). When blink

mode is enabled, the state of the blink flip flag sets the

phase, and the output ports are set by either the blink

phase 0 register or the blink phase 1 register (Table 7).

The blink mode is disabled by clearing the blink enable

flag E in the configuration register (Table 4). When blink

mode is disabled, the blink phase 0 register alone con-

trols the output ports.

Blink Phase Registers

When the blink function is disabled, the blink phase 0

P7) when configured as outputs (Table 8). A duplicate

the blink function is enabled (Table 9). A logic high sets

the appropriate output port high impedance, while a

logic low makes the port go low.

MAX7315

8-Port I/O Expander with LED Intensity

Control and Interrupt

______________________________________________________________________________________ 15

Table 4. Configuration register (continued)

ADDRESS

CODE

(HEX)

D7 D6 D5 D4 D3 D2 D1 D0

CONFIGURATION

R/W

INTERRUPT

STATUS

—

INTERRUPT

OUTPUT

CONTROL

AS GPO

INTERRUPT

ENABLE

GLOBAL

INTENSITY

BLINK FLIP

BLINK

ENABLE

Disable data change interrupt—INT/O8

output is controlled by the O0 and O1 bits

— INT

O0 I G B E

Enable data change interrupt—INT/O8

output is controlled by port input data

change

—

XXXX1 XXX

INT/O8 output is low (blink is disabled)

—

XXX00XX0

INT/O8 output is high impedance (blink is

disabled)

—

XXX10XX0

IN T/O8 outp ut i s l ow d ur i ng b l i nk p hase 0

—

XXX00XX1

INT/O8 output is high impedance during

blink phase 0

—

XXX10XX1

IN T/O8 outp ut i s l ow d ur i ng b l i nk p hase 1

—

XX0 X 0 XX1

INT/O8 output is high impedance during

blink phase 1

—

XX1 X 0 XX1

Read-back data change interrupt status

—data change is not detected, and

INT/O8 output is high when interrupt

enable (I bit) is set

0 0XXXXXX

Read-back data change interrupt status

—data change is detected, and INT/O8

output is low when interrupt enable (I bit)

is set

0x0F

1 0XXXXXX

1 2 ... 10 11 12 13 14 15 16 17 18 19 20 ... 26 27

Control and Interrupt 1

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