General DescriptionThe MAX6960–MAX6963 are compact cathode-row dis-play drivers that interface microprocessors to 8 x 8 dot-matrix red, green, and yel
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Initial Power-UpOn power-up, all control registers are reset (Table 12),and the MAX6960 defaults to driver address 0 within apanel of 256 drivers, mon
MAX6960–MAX6963The global driver devices register should be writtenwith the total number of MAX6960s interconnected onthe 3-wire interface, minus 1 (T
Invert Pixels (Bit D1)The invert pixels (IP) bit in the global panel configura-tion register controls whether the display memory isused directly or in
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arithmetic (off, 1/3, 2/3, full) or geometric (off, 1/4, 1/2,full). The setting is made on a digit-by-digit basis, soeach color on an RGY or RGB panel
MAX6960–MAX6963255/256 digit intensity multiplied by the maximum255/256 panel intensity. The minimum interdigit blank-ing time is therefore 4/256 of a
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MAX6960–MAX6963Global Clear Planes CommandWriting the global clear planes counter (Table 31) allowsany or all display memory planes to be cleared with
of the LED drive current of 40mA is guaranteed over asupply range of 3.15V to 3.6V.Bypass each of the 5 V+ power-supply pins to GNDwith a 0.1µF capaci
MAX6960–MAX6963the supply bus at least every several MAX6960s. EachMAX6960 draws a peak current of either 40mA x 16segments = 640mA (current setting =
Connecting Multiple MAX6960s to the 4-Wire BusUp to 256 MAX6960s can be interconnected to sharethe same 4-wire bus in parallel, sharing a common CS.Th
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32, 44, 48L QFN.EPSeLeLA1AA2E/2ED/2DDETAIL AD2/2D2bLkE2/2E2(NE-1) X e(ND-1) X eeCLCLCLCLkDETAIL BeLL1PROPRIETARY INFORMATIONDOCUMENT CONTROL NO.APPR
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