
MAX6960–MAX6963
4-Wire Serially Interfaced
8 x 8 Matrix Graphic LED Drivers
22 ______________________________________________________________________________________
REGISTER DATA
REGISTER
ADDRESS
CODE (HEX)
D7 D6 D5 D4 D3 D2 D1
Display panel is built with monocolor or RGB
digits (permanently set this way for MAX6962 and
MAX6963)
0x0D PI 0 F R
DP1 DP0 IP
S
Display panel is built with RGY digits
0x0D PI 1 F R
DP1 DP0 IP
Table 21. Global Panel Configuration—Color Control (C Data Bit D6) Format
REGISTER DATA
REGISTER
ADDRESS
CODE (HEX)
D7 D6 D5 D4 D3 D2 D1
Four display memory planes (0, 1, 2, 3) available;
pixel level-intensity control is 1 bit per pixel per
color (on/off) (permanently set this way for
MAX6961 and MAX6963)
0x0D 0 C F R
DP1 DP0 IP
S
Two display memory planes (0, 1) available;
pixel level-intensity control is 2 bits per pixel per
color (4 levels)
0x0D 1 C F R
DP1 DP0 IP
Table 22. Global Panel Configuration—Planes/Intensity Control (PI Data Bit D7) Format
PATTERN OF MULTIPLEX CYCLES
FOR WHICH A PIXEL IS ENABLED
PIXEL
GRADUATION
PIXEL
DATA
PIXEL
INTENSITY
SETTING
012345678910
11111111111
10110110110
10101010101
01001001001
01000100010
00000000000
Table 23. Frame Modulation with Pixel Intensity
PATTERN OF MULTIPLEX CYCLES
FOR WHICH A PIXEL IS ENABLED
PIXEL
GRADUATION
PIXEL
DATA
PIXEL
INTENSITY
SETTING
012345678910
11111111111
10110110110
10101010101
01001001001
01000100010
00000000000
Table 24. Pixel Intensity Scale Register Format
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