1 of 15 041202 Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisio
DS1682 10 of 15 The DS1682 can operate in the following two modes: 1) Slave Receiver Mode (DS1682 Write Mode): Serial data and clock are received
DS1682 11 of 15 ABSOLUTE MAXIMUM RATINGS* Voltage Range on Any Pin Relative to Ground -0.3V to +6V Operating Temperature Range -40°C to +85°C
DS1682 12 of 15 AC ELECTRICAL CHARACTERISTICS (-40°C to +85°C; VCC = 2.5V to 5.5V) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES EEPRO
DS1682 13 of 15 Figure 7. TIMING DIAGRAM NOTES: 1) VCC must be at or above 2.5V for tEW after the end of an event to insure data transfer to th
DS1682 14 of 15 Figure 8. TOTAL RUN TIME Figure 8 shows the DS1682 measuring total run time and operating from a battery with the alarm tied to
DS1682 15 of 15 Figure 10. TOTAL TIME-OF-USE APPLICATION WITH SLOW VCC SLEW RATE Figure 10 shows the DS1682 in a total time-of-use application wi
DS1682 2 of 15 OPERATION The block diagram in Figure 1 shows the relationship between the major functional blocks, the serial interface, and the EEP
DS1682 3 of 15 SIGNAL DESCRIPTIONS VCC – VCC is a +2.5V to +5.5V input supply. GND – Ground. SCL (2-Wire Serial-Clock Input) – The SCL pin is th
DS1682 4 of 15 Figure 2. MEMORY MAP ADDR BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 FUNCTION 00 0 AF WDF WMDF AOS RE AP ECMSB Configu
DS1682 5 of 15 EVENT LOGGING When the DS1682 is powered up, the event time and count values recorded in the EEPROM are transferred to the ETC and e
DS1682 6 of 15 ALARM The alarm register is a 32-bit register that holds time in quarter-second resolution. When a nonzero number is programmed into
DS1682 7 of 15 CONFIGURATION REGISTER MSb LSb 0 AF WDF WMDF AOS RE AP ECMSB Note: The configuration register is not stored in EEPROM until a
DS1682 8 of 15 2-WIRE SERIAL DATA BUS The DS1682 supports a bidirectional, 2-wire bus and data-transmission protocol. A device that sends data onto
DS1682 9 of 15 Accordingly, the following bus conditions have been defined: Bus Not Busy: Both data and clock lines remain HIGH. Start Data Trans
Comentários a estes Manuais