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manuais Rainbow-electronics DS3170

Manuais de instruções e guias do utilizador para Comunicação Rainbow-electronics DS3170.
Disponibilizamos 1 manuais Rainbow-electronics DS3170 em pdf para descarga gratuita: Manual do Utilizador


Rainbow electronics DS3170 Manual do Utilizador (233 páginas)


Marca: Rainbow-electronics | Categoria: Comunicação | Tamanho: 1.87 MB |

 

Índice

DS3/E3 Single-Chip Transceive

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DETAILED DESCRIPTION

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1 BLOCK DIAGRAMS

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Figure 1-2. Block Diagram

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TABLE OF CONTENTS

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18 REVISION HISTORY 233

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2 APPLICATIONS

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3 FEATURE DETAILS

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4 STANDARDS COMPLIANCE

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5 ACRONYMS AND GLOSSARY

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6 MAJOR OPERATIONAL MODES

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6.5 DS3/E3 Framed UNI Mode

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7 PIN DESCRIPTIONS

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7.3 Pin Functional Timing

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Figure 7-30. 8-Bit Mode Read

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9 FUNCTIONAL DESCRIPTION

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9.1.8 Interrupt Structure

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9.2 Clocks

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Table 9-1. LIU Enable Table

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PORT.CR3

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LOOPBACK

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DIAGNOSTIC

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9.3 Reset and Power-Down

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Figure 9-5. Reset Sources

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9.4 Global Resources

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Figure 9-6. 8KREF Logic

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9.5 Port Resources

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Figure 9-9. Loopback Modes

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Figure 9-10. ALB Mux

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9.5.3 AIS Logic

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LINE/TRIBUTARY

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TRUNK SIDE

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9.5.4 Loop Timing Mode

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9.5.6 Trail Trace

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9.5.7 BERT

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9.5.8 System Port Pins

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9.5.9 Framing Modes

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9.5.10 Line Interface Modes

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9.6.1 General Description

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9.6.2 Features

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9.6.3 Transmit Formatter

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9.6.4 Receive Framer

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1524 Bit Payload

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384 bits

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9.7.1 General Description

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9.7.2 Features

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9.7.3 Transmit FIFO

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9.8 Trail Trace Controller

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9.8.2 Features

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9.8.3 Functional Description

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9.8.4 Transmit Data Storage

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9.8.9 Receive Data Storage

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9.9.1 General Description

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9.9.2 Features

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9.9.3 Functional Description

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9.10 Line Encoder/Decoder

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9.10.2 Features

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9.10.3 B3ZS/HDB3 Encoder

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9.10.6 B3ZS/HDB3 Decoder

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Figure 9-25. B3ZS Signatures

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Figure 9-26. HDB3 Signatures

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9.11.1 General Description

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9.11.2 Features

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LoadVerify

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MatchVerify

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9.12.1 General Description

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9.12.2 Features

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9.12.3 Detailed Description

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9.12.4 Transmitter

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9.12.5 Receiver

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INT pin if enabled

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10 OVERALL REGISTER MAP

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11.1 Registers Bit Maps

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11.1.3 T3 Register Bit Map

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11.2 Global Registers

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INT pin will be driven low

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INT pin

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11.3 Port Register

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RST and the GL.CR1.RST bit

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11.4 BERT

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11.6 HDLC

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11.7 FEAC Controller

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11.8 Trail Trace

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12 JTAG INFORMATION

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12.4 JTAG ID Codes

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Table 12-2. JTAG ID Codes

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12.6 IO Pins

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13 PIN CONFIGURATIONS

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14 PACKAGE INFORMATION

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Table 16-3. Output Pin Drive

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17 AC TIMING CHARACTERISTICS

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17.3.1 SPI Bus Mode

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17.3.2 Parallel Bus Mode

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17.5.1 Waveform Templates

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18 REVISION HISTORY

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Tabla de contenidos

DGS-6600

1

Chassis Based Switches

2

Technical Specifications

3

Software Features

4

Optional Products

6




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