Rainbow-electronics DS3131 Manual do Utilizador Página 99
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Figure 9-10. Transmit DMA Operation
00h
08h
Done-Queue Descriptors
(circular queue)
04h
Free Desc. Ptr.CH#5Status
Free Desc. Ptr.CH#1Status
Free Desc. Ptr.CH#Status
00h
Pending-Queue Descriptors
(circular queue)
04h
Free Desc. Ptr.CH#5PRI
Free Desc. Ptr.CH#1PRI
Data Buffer Address
CH #1
EOF
Last Transmitted
Data Buffe
r
for Channel 1
# Bytes Next Desc. Ptr.
Next Pend. Desc.P
V
CV
unused
unused
Data Buffer Address
CH #1
EOF
2nd Transmitted
Data Buffe
r
for Channel 1
# Bytes Next Desc. Ptr.
Next Pend. Desc.P
V
CV
unused
unused
Data Buffer Address
CH #1
EOF
1st Transmitted
Data Buffe
r
for Channel 1
# Bytes Next Desc. Ptr.
Next Pend. Desc.P
V
CV
unused
unused
Data Buffer Address
CH #5
EOF
1st Queued
Data Buffe
r
for Channel 5
# Bytes Next Desc. Ptr.
Next Pend. Desc.P
V
CV
unused
unused
Data Buffer Address
CH #5
EOF
2nd Queued
Data Buffe
r
for Channel 5
# Bytes Next Desc. Ptr.
Next Pend. Desc.P
V
CV
unused
unused
Data Buffer Address
CH #5
EOF
Last Queued
Data Buffe
r
for Channel 5
# Bytes Next Desc. Ptr.
Next Pend. Desc.P
V
CV
unused
unused
Data Buffer Address
CH #1
EOF
Queued
Data Buffe
r
for Channel 1
# Bytes Next Desc. Ptr.
Next Pend. Desc.P
V
CV
unused
unused
Open Descriptor Space
A
vailable for Use by the Hos
t
Data Buffer Address
CH #5
EOF
Transmitted
Data Buffe
r
for Channel 5
# Bytes Next Desc. Ptr.
Next Pend. Desc.P
V
CV
unused
unused
08h
0Ch
Free Desc. Ptr.CH#PRI
Free Desc. Ptr.CH#PRI
Open Descriptor Space
A
vailable for Use by the Hos
t
0Ch
14h
10h
Free Desc. Ptr.CH#Status
Free Desc. Ptr.CH#Status
Free Desc. Ptr.CH#Status
EOF = 0
EOF = 0
EOF = 1
EOF = 0
EOF = 1
EOF = 0
EOF = 0
EOF = 1
- DS3131 BoSS 1
- 40-Port, Unchannelized 1
- TABLE OF CONTENTS 2
- 3 of 174 3
- LIST OF FIGURES 4
- LIST OF TABLES 5
- 1. MAIN FEATURES 6
- 2. DETAILED DESCRIPTION 7
- 8 of 174 8
- 9 of 174 9
- Figure 2-1. Block Diagram 10
- 11 of 174 11
- Table 2-A. Restrictions 12
- 13 of 174 13
- 3. SIGNAL DESCRIPTION 14
- 3.1 Overview/Signal List 14
- Signal Naming Convention 14
- Figure 3-1. Signal Floorplan 19
- 20 of 174 20
- 21 of 174 21
- 22 of 174 22
- 3.4 JTAG Signal Description 23
- 24 of 174 24
- 25 of 174 25
- 3.6 PCI Extension Signals 26
- 27 of 174 27
- 4. MEMORY MAP 28
- 4.1 Introduction 28
- 29 of 174 29
- 30 of 174 30
- 31 of 174 31
- 32 of 174 32
- 4.7 BERT Registers (5xx) 33
- 4.10 FIFO Registers (9xx) 34
- 35 of 174 35
- 36 of 174 36
- 37 of 174 37
- 38 of 174 38
- 5.3 Status and Interrupt 39
- 40 of 174 40
- 41 of 174 41
- 42 of 174 42
- at the PCI bus 43
- 44 of 174 44
- 0 = interrupt masked 45
- 46 of 174 46
- 6. LAYER 1 47
- 6.1 General Description 47
- 48 of 174 48
- 49 of 174 49
- 50 of 174 50
- 6.3 BERT 51
- Figure 6-2. BERT Mux Diagram 51
- 52 of 174 52
- 53 of 174 53
- 54 of 174 54
- 55 of 174 55
- 56 of 174 56
- 57 of 174 57
- 58 of 174 58
- 7. HDLC 59
- 7.1 General Description 59
- 7.2 HDLC Operation 59
- 60 of 174 60
- 61 of 174 61
- 62 of 174 62
- 63 of 174 63
- 64 of 174 64
- 8. FIFO 65
- Figure 8-1. FIFO Example 66
- 8.1.1 Receive High Watermark 67
- 8.1.2 Transmit Low Watermark 67
- 68 of 174 68
- 69 of 174 69
- 70 of 174 70
- 71 of 174 71
- 72 of 174 72
- 73 of 174 73
- 9.1 Introduction 74
- 75 of 174 75
- 9.2 Receive Side 76
- 9.2.1 Overview 76
- 77 of 174 77
- 78 of 174 78
- 79 of 174 79
- 9.2.2 Packet Descriptors 80
- 81 of 174 81
- 9.2.3 Free Queue 82
- Calculation 83
- 85 of 174 85
- 86 of 174 86
- 9.2.4 Done Queue 87
- 88 of 174 88
- 89 of 174 89
- 90 of 174 90
- 91 of 174 91
- 92 of 174 92
- 9.2.5 DMA Configuration RAM 93
- 94 of 174 94
- 95 of 174 95
- 96 of 174 96
- 9.3 Transmit Side 97
- 9.3.1 Overview 97
- 98 of 174 98
- 99 of 174 99
- 100 of 174 100
- 101 of 174 101
- 102 of 174 102
- 103 of 174 103
- 104 of 174 104
- 9.3.2 Packet Descriptors 105
- 106 of 174 106
- 9.3.3 Pending Queue 107
- 108 of 174 108
- 109 of 174 109
- 110 of 174 110
- 9.3.4 Done Queue 111
- 112 of 174 112
- 113 of 174 113
- 114 of 174 114
- 115 of 174 115
- 9.3.5 DMA Configuration RAM 116
- 117 of 174 117
- 118 of 174 118
- 119 of 174 119
- 120 of 174 120
- 10. PCI BUS 121
- 10.1.1 PCI Read Cycle 122
- Figure 10-2. PCI Bus Read 122
- 10.1.2 PCI Write Cycle 123
- Figure 10-3. PCI Bus Write 123
- 10.1.3 PCI Bus Arbitration 124
- 10.1.4 PCI Initiator Abort 124
- 10.1.5 PCI Target Retry 125
- 10.1.7 PCI Target Abort 126
- 127 of 174 127
- 128 of 174 128
- 10.2.1 Command Bits (PCMD0) 129
- 10.2.2 Status Bits (PCMD0) 130
- 131 of 174 131
- 132 of 174 132
- 133 of 174 133
- 10.2.3 Command Bits (PCMD1) 134
- 10.2.4 Status Bits (PCMD1) 135
- Register Name: PLTH1 136
- PF TYPE1 TYPE0 MSI 137
- 11. LOCAL BUS 138
- 11.1 General Description 138
- DS3131 BOSS 139
- 11.1.1 PCI Bridge Mode 141
- Setting 141
- 11.1.2 Configuration Mode 143
- 144 of 174 144
- 145 of 174 145
- 146 of 174 146
- 148 of 174 148
- Intel Mode (LIM = 0) 149
- LRDYLRDY 149
- LRDY (LRDY = 0000) 149
- 151 of 174 151
- 152 of 174 152
- Motorola Mode (LIM = 1) 154
- 12. JTAG 155
- 12.1 JTAG Description 155
- Figure 12-1. Block Diagram 155
- 156 of 174 156
- 157 of 174 157
- 158 of 174 158
- 159 of 174 159
- 12.4 Test Registers 160
- 13. AC CHARACTERISTICS 161
- ABSOLUTE MAXIMUM RATINGS 161
- DC CHARACTERISTICS 161
- 165 of 174 165
- (continued) 166
- 14. MECHANICAL DIMENSIONS 169
- 14.1 272 PBGA Package 169
- 15. APPLICATIONS 170
- 171 of 174 171
- 172 of 174 172
- 173 of 174 173
- 15.3 ONET/SDH Applications 174
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