Rainbow-electronics DS2153Q Manual do Utilizador

Copyright 1995 by Dallas Semiconductor Corporation.All Rights Reserved. For important information regardingpatents and other intellectual property r

DS2153Q022697 10/48TSA1 TCR1.2 Transmit Signaling All Ones. 0=normal operation 1=force timeslot 16 in every frame to all onesTSM TCR1.1 TSYNC Mode Sel

DS2153Q022697 11/48THDB3 CCR1.6 Transmit HDB3 Enable. 0=HDB3 disabled 1=HDB3 enabledTG802 CCR1.5 Transmit G.802 Enable. See Section 13 for details. 0

DS2153Q022697 12/48RSERC CCR2.3 RSER Control. 0=allow RSER to output data as received under all conditions 1=force RSER to one under loss of frame ali

DS2153Q022697 13/48applied and is stable. Must be set and cleared again for a subsequentreset. Do not leave this bit set high.LIRST CCR3.3 Line Inter

DS2153Q022697 14/48RIR: RECEIVE INFORMATION REGISTER (Address=08 Hex)(MSB) (LSB)TESF TESE JALT RESF RESE CRCRC FASRC CASRCSYMBOL POSITION NAME AND DES

DS2153Q022697 15/48CRC4 SYNC COUNTERThe CRC4 Sync Counter increments each time the 8 msCRC4 multiframe search times out. The counter iscleared when t

DS2153Q022697 16/48ALARM CRITERIA Table 4–1ALARM SET CRITERIA CLEAR CRITERIACCITTSPEC.RSA1(receive signalingall ones)over 16 consecutive frames (one

DS2153Q022697 17/48IMR1: INTERRUPT MASK REGISTER 1 (Address=16 Hex)(MSB) (LSB)RSA1 RDMA RSA0 RSLIP RUA1 RRA RCL RLOSSYMBOL POSITION NAME AND DESCRIPTI

DS2153Q022697 18/48IMR2: INTERRUPT MASK REGISTER 2 (Address=17 Hex)(MSB) (LSB)RMF RAF TMF SEC TAF LOTC RCMF TSLIPSYMBOL POSITION NAME AND DESCRIPTIONR

DS2153Q022697 19/48VCR1: UPPER BIPOLAR VIOLATION COUNT REGISTER 1 (Address=00 Hex)VCR2: LOWER BIPOLAR VIOLATION COUNT REGISTER 2 (Address=01 Hex) (

DS2153Q022697 2/48attenuator (selectable to either 32 bits or 128 bits) canbe placed in either the transmit or receive data paths.The framer locates t

DS2153Q022697 20/48EBCR1: E–BIT COUNT REGISTER 1 (Address=04 Hex) EBCR2: E–BIT COUNT REGISTER 2 (Address=05 Hex) (MSB) (LSB)(note 1)(note 1) (note

DS2153Q022697 21/48additional bits from the TLINK pin. If the user wishes topass the Sa bits through the DS2153Q without thembeing altered, then the

DS2153Q022697 22/48conditions. Their validity should be qualified by check-ing for synchronization at the CAS level. In CCS signal-ing mode, RS1 to

DS2153Q022697 23/48will be informed when the signaling registers need to beloaded with data. The user has 2 ms to load the databefore the old data wi

DS2153Q022697 24/489.0 CLOCK BLOCKING REGISTERSThe Receive Channel Blocking Registers(RCBR1/RCBR2/RCBR3/RCBR4) and the TransmitChannel Blocking Regist

DS2153Q022697 25/48TCBR1/TCBR2/TCBR3/TCBR4: DEFINITION WHEN CCR3.6 = 1 (MSB) (LSB)CH20CH4 CH19 CH3 CH18 CH2 CH17* CH1*CH24 CH8 CH23 CH7 CH22 CH6 C

DS2153Q022697 26/48RAF: RECEIVE ALIGN FRAME REGISTER (Address=2F Hex)(MSB) (LSB)Si 0 0 1 1 0 1 1SYMBOL POSITION NAME AND DESCRIPTIONSi RAF.7 Internati

DS2153Q022697 27/481 TAF.3 Frame Alignment Signal Bit.0 TAF.2 Frame Alignment Signal Bit.1 TAF.1 Frame Alignment Signal Bit.1 TAF.0 Frame Alignment Si

DS2153Q022697 28/48DJA LICR.1 Disable Jitter Attenuator. 0=jitter attenuator enabled 1=jitter attenuator disabledTPD LICR.0 Transmit Power Down. 0=nor

DS2153Q022697 29/48LINE BUILD OUT SELECT IN LICR Table 12–2L2 L1 L0 APPLICATION TRANSFORMER RETURN LOSS Rt0 0 0 75 ohm normal 1:1.15 step–up NM 0 ohm

DS2153Q022697 3/48DS2153Q BLOCK DIAGRAM Figure 1–1RCLKRLINKRLCLKRCHBLKRCHCLKRSERSYSCLKRSYNCTCLKTSERTSYNCTCHCLKTCHBLKCS WR(R/W) RD(DS) ALE(AS) AD0 – AD

DS2153Q022697 30/48DS2153Q will divide the attached crystal by either 3.5 or4.5 instead of the normal 4 to keep the buffer from over-flowing. When th

DS2153Q022697 31/48DS2153Q JITTER TOLERANCE Figure 12–2MINIMUM TOLERANCELEVEL AS PERITU G.823DS2153QTOLERANCE10 100 1K 10K 100K11K1001010.11.50.24020

DS2153Q022697 32/48DS2153Q JITTER ATTENUATION Figure 12–4ITU G.7XXPROHIBITED AREA1 10 100 1K 10K 100KFREQUENCY (Hz)0 dB–20 dB–40 dB–60 dBJITTER ATTENU

DS2153Q022697 33/48RECEIVE SIDE BOUNDARY TIMING (WITH ELASTIC STORES DISABLED) Figure 13–2RCLKRSERRSYNCRCHCLKRCHBLK1RLCLK2RLINKLSBMSB MSBCHANNEL 32 CH

DS2153Q022697 34/481.544 MHz BOUNDARY TIMING WITH ELASTIC STORE(S) ENABLED Figure 13–3SYSCLKRSER1,RSYNC2RSYNC3RCHCLKRCHBLK4CHANNEL 24/32 CHANNEL 1/2CH

DS2153Q022697 35/48TRANSMIT SIDE TIMING Figure 13–515 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15FRAME#1612345614TSYNC1TSYNC2TCLK3TLINK3NOTES:1. TSYNC in t

DS2153Q022697 36/48TRANSMIT SIDE BOUNDARY TIMING Figure 13–6TCLKTSERTSYNC1TSYNC2TCHCLKCHANNEL 2CHANNEL 1TCHBLK3TLCLK4TLINK4Don’t CareLSB Si 1 A Sa4 Sa

DS2153Q022697 37/48G.802 TIMING Figure 13–7TIMESLOT# 30 31 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 2

DS2153Q022697 38/48DS2153Q SYNCHRONIZATION FLOWCHART Figure 13–8POWER UPRLOS=1FAS SYNCSYNC DECLAREDCRITERIA METFASSA=0CAS MULTIFRAMESEARCH (IF ENABLED

= REGISTER= DEVICE PIN= SELECTORKEYTSERTLINKTS1 TO TS16AISGENERATIONTRANSMIT SIGNALLINGALL ONES(TCR1.2)TTIP,TRINGTAFTNAFTIMESLOT 0PASS–THROUGH(TCR1.6)

DS2153Q022697 4/48PIN DESCRIPTION Table 1–1PIN SYMBOL TYPE DESCRIPTION1234AD4AD5AD6AD7I/O Address/Data Bus. A 8–bit multiplexed address/data bus.5 R

DS2153Q022697 40/48ABSOLUTE MAXIMUM RATINGS*Voltage on Any Pin Relative to Ground –1.0V to +7.0VOperating Temperature 0°C to 70°C (–40°C to +85°C for

DS2153Q022697 41/48AC CHARACTERISTICS – PARALLEL PORT (0°C to 70°C; VDD=5V + 5%)(–40°C to +85°C; VDD=5V +5%/–4% for DS2153QN)PARAMETER SYMBOL MIN TYP

DS2153Q022697 42/48INTEL READ BUS AC TIMING Figure 14–1ALEWRRDCSAD0-AD7tCYCPWASHPWEHtASDtASEDtASLtDDRtCHtDHRtASDtCStAHLPWELINTEL WRITE BUS AC TIMING

DS2153Q022697 43/48MOTOROLA BUS AC TIMING Figure 14–3ASDSR/WAD0-AD7(READ)CSAD0-AD7(WRITE)PWASHPWELtCYCtRWStASDtRWHtDDRtDHRtCHtCStAHLtASLtDHWtDSWtAHLt

DS2153Q022697 44/48AC CHARACTERISTICS – RECEIVE SIDE (0°C to 70°C; VDD=5V ± 5%)(–40°C to +85°C; VDD=5V +5%/–4% for DS2153QN)PARAMETER SYMBOL MIN TYP M

DS2153Q022697 45/48RECEIVE SIDE AC TIMING Figure 14–4RCLKRSERRCHCLKRCHBLKRSYNC1RSYNC2RLCLK3RLINK3tD5tCLtCHtCPtSUtD4tPWtD3tDDMSB OFSYSCLKtRtFtSLtSHtSPC

DS2153Q022697 46/48AC CHARACTERISTICS – TRANSMIT SIDE (0°C to 70°C; VDD=5V + 5%)(–40°C to +85°C; VDD=5V +5%/–4% for DS2153QN)PARAMETER SYMBOL MIN TYP

DS2153Q022697 47/48TRANSMIT SIDE AC TIMING Figure 14–5TCLKTSER4TCHCLKTCHBLKTSYNC1TSYNC2TLCLK3TLINK3tRtFtCLtPtCHtSUtHDtD1tD2tD3tPWtSUtD4tHDtSUMSBLSBNOT

DS2153Q022697 48/48DS2153Q E1 SINGLE–CHIP TRANSCEIVER 44–PIN PLCCCA1A2 ABB1.075 MAXN1.150MAXNOTE 1D1DCH1EE1e1E2D2NOTE1: PIN 1 IDENTIFIER TO BE LOCATE

DS2153Q022697 5/48PIN DESCRIPTIONTYPESYMBOL20 BTS I Bus Type Select. Strap high to select Motorola bus timing; strap low toselect Intel bus timing.

DS2153Q022697 6/48PIN DESCRIPTIONTYPESYMBOL40 TCHCLK O Transmit Channel Clock. 256 KHz clock which pulses high during the LSBof each channel. Useful

DS2153Q022697 7/48ADDRESS REGISTER NAMER/WADDRESSREGISTER NAMER/W30 R Receive Signaling 1 40 R/W Transmit Signaling 131 R Receive Signaling 2 41 R/W T

DS2153Q022697 8/48RCR1: RECEIVE CONTROL REGISTER 1 (Address=10 Hex)(MSB) (LSB)RSMF RSM RSIO – – FRC SYNCE RESYNCSYMBOL POSITION NAME AND DESCRIPTIONRS

DS2153Q022697 9/48RCR2: RECEIVE CONTROL REGISTER 2 (Address=11 Hex)(MSB) (LSB)Sa8S Sa7S Sa6S Sa5S Sa4S RSCLKM RESE –SYMBOL POSITION NAME AND DESCRIPTI