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AT84AD004

5390A–BDC–06/04

Digital Output Coding (Nominal Settings)

Pin Description

Table 7. Digital Output Coding (Nominal Setting)

Differential

Analog Input

Voltage Level

Digital Output

I or Q (Binary Coding)

Out-of-range Bit

> 250 mV > Positive full-scale + 1/2 LSB 1 1 1 1 1 1 1 1 1

250 mV

248 mV

Positive full-scale + 1/2 LSB

Positive full-scale - 1/2 LSB

1 1 1 1 1 1 1 1

1 1 1 1 1 1 1 0

1 mV

-1 mV

Bipolar zero + 1/2 LSB

Bipolar zero - 1/2 LSB

1 0 0 0 0 0 0 0

0 1 1 1 1 1 1 1

-248 mV

-250 mV

Negative full-scale + 1/2 LSB

Negative full-scale - 1/2 LSB

0 0 0 0 0 0 0 1

0 0 0 0 0 0 0 0

< -250 mV < Negative full-scale - 1/2 LSB 0 0 0 0 0 0 0 0 1

Table 8. AT84AD004 LQFP 144 Pin Description

Symbol Pin number Function

GNDA, GNDD, GNDO

10, 12, 22, 24, 36, 38, 40, 42, 44, 46, 51,

54, 59, 61, 63, 65, 67, 69, 85, 87, 97, 99,

109, 111, 130, 142, 144

Ground pins. To be connected to external

ground plane

CCA

41, 43, 45, 60, 62, 64 Analog positive supply: 3.3V typical

CCD

9, 21, 37, 39, 66, 68, 88, 100, 112, 123,

141

3.3V digital supply

CCO

11, 23, 86, 98, 110, 143

2.25V output and 3-wire serial interface

supply

INI

57, 58

In-phase (+) analog input signal of the

sample & hold differential preamplifier

channel I

INIB

55, 56

Inverted phase (-) of analog input signal

INI

)

INQ

47, 48

In-phase (+) analog input signal of the

sample & hold differential preamplifier

channel Q

INQB

49, 50

Inverted phase (-) of analog input signal

INQ

)

CLKI 124 In-phase (+) clock input signal

CLKIN 125

Inverted phase (-) clock input signal

(CLKI)

CLKQ 129 In-phase (+) clock input signal

1 2 ... 15 16 17 18 19 20 21 22 23 24 25 ... 57 58

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