Rainbow-electronics T89C5115 Manual do Utilizador Página 1

Rev. 4128A–8051–04/021Features• 80C51 Core Architecture• 256 Bytes of On-chip RAM• 256 Bytes of On-chip ERAM– 16-KB of On-chip Flash Memory– Data Rete

10T89C51154128A–8051–04/02T2CON C8hTimer/Counter 2controlTF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2# CP/RL2#T2MOD C9hTimer/Counter 2Mode––––––T2OEDCENRCAP2H CB

100T89C51154128A–8051–04/02Package DrawingSOIC28

101T89C51154128A–8051–04/02Package DrawingVQFP32

iT89C51154128A–8051–04/02Table of ContentsFeatures ... 1

iiT89C51154128A–8051–04/02In-System Programming (ISP) ... 38Flash Programming and Erasure...

iiiT89C51154128A–8051–04/02Voltage Conversion ... 80Clock Sel

Printedonrecycledpaper.ATMEL®, is a registered trademarkof Atmel.Other terms and product names may be the trademarks of others.© Atmel Corporation 200

11T89C51154128A–8051–04/02Table 8. Interrupt SFRsMnemonicAddName 76543210IEN0 A8hInterrupt EnableControl 0EA EC ET2 ES ET1 EX1 ET0 EX0IEN1 E8hInterrup

12T89C51154128A–8051–04/02ReservedNote: 1. These registers are bit-addressable.Sixteen addresses in the SFR space are both byte-addressable and bit-ad

13T89C51154128A–8051–04/02Clock The T89C5115 core needs only 6 clock periods per machine cycle. This feature, called‘X2’, provides the following advan

14T89C51154128A–8051–04/02Figure 3. Clock CPU Generation DiagramXTAL1XTAL2PDPCON.1CPU Core10÷ 2PERIPHCLOCKClockPeripheral Clock SymbolCPUCLOCKCPU Core

15T89C51154128A–8051–04/02Figure 4. Mode Switching WaveformsNote: In order to prevent any incorrect operation while operating in the X2 mode, users mu

16T89C51154128A–8051–04/02Register Table 12. CKCON RegisterCKCON (S:8Fh)Clock Control RegisterNotes: 1. This control bit is validated when the CPU clo

17T89C51154128A–8051–04/02Power ManagementIntroduction Two power reduction modes are implemented in the T89C5115: the Idle mode and thePower-down mode

18T89C51154128A–8051–04/02Idle Mode Idle mode is a power reduction mode that reduces the power consumption. In this mode,program execution halts. Idle

19T89C51154128A–8051–04/02Exiting Power-down Mode Note: If VDD was reduced during the Power-down mode, do not exit Power-down mode untilVDD is restore

2T89C51154128A–8051–04/02In X2 mode a maximum external clock rate of 20 MHz reaches a 300 ns cycle time.Block DiagramNotes: 1. 8 analog Inputs/8 Digit

20T89C51154128A–8051–04/02Registers PCON (S:87h)Table 14. PCON RegisterPower Configuration RegisterReset Value = XXXX 0000b76543210––––GF1GF0PDIDLBitN

21T89C51154128A–8051–04/02Data Memory The T89C5115 provides data memory access in two different spaces:The internal space mapped in three separate seg

22T89C51154128A–8051–04/02Figure 8. Lower 128 bytes Internal RAM OrganizationUpper 128 Bytes RAM The upper 128 bytes of RAM are accessible from addres

23T89C51154128A–8051–04/02Dual Data PointerDescription The T89C5115 implements a second data pointer for speeding up code execution andreducing code s

24T89C51154128A–8051–04/02Registers Table 16. PSW RegisterPSW (S:8Eh)Program Status Word RegisterReset Value = 0000 0000b76543210CY AC F0 RS1 RS0 OV F

25T89C51154128A–8051–04/02Table 17. AUXR1 RegisterAUXR1 (S:A2h)Auxiliary Control Register 1Reset Value = xxxx 00x0b76543210– – ENBOOT – GF3 0 – DPSBit

26T89C51154128A–8051–04/02EEPROM DataMemoryThe 2-kbyte on-chip EEPROM memory block is located at addresses 0000h to 07FFh ofthe XRAM/ERAM memory space

27T89C51154128A–8051–04/02Examples ;*F*************************************************************************;* NAME: api_rd_eeprom_byte;* DPTR cont

28T89C51154128A–8051–04/02Registers Table 18. EECON RegisterEECON (S:0D2h)EEPROM Control RegisterReset Value = XXXX XX00bNot bit addressable76543210EE

29T89C51154128A–8051–04/02Program/CodeMemoryThe T89C5115 implement 16-KB of on-chip program/code memory.The Flash memory increases EPROM and ROM funct

3T89C51154128A–8051–04/02Pin ConfigurationP3.4/T0P3.3/INT1P4.11P3.7P3.2/INT0P1.5/AN5P1.7/AN7P1.6/AN6P2.0VAREFVAVCCVAGNDP1.0/AN0/T2P1.1/AN1/T2EXP1.2/AN

30T89C51154128A–8051–04/02FM0 Memory Architecture The Flash memory is made up of 4 blocks (see Figure 11):1. The memory array (user space) 16-KB.2. Th

31T89C51154128A–8051–04/02Overview of FM0OperationsThe CPU interfaces to the Flash memory through the FCON register and AUXR1register.These registers

32T89C51154128A–8051–04/02Interrupts that may occur during programming time must be disabled to avoid any spuri-ous exit of the programming mode.Statu

33T89C51154128A–8051–04/02Figure 12. Column Latches Loading ProcedureNote: The last page address used when loading the column latch is the one used to

34T89C51154128A–8051–04/02Figure 13. Flash and Extra row Programming ProcedureHardware Security ByteThe following procedure is used to program the Har

35T89C51154128A–8051–04/02Figure 14. Hardware Programming ProcedureReading the Flash SpacesUser The following procedure is used to read the User space

36T89C51154128A–8051–04/02Figure 15. Reading ProcedureFlash Protection from ParallelProgrammingThe three lock bits in Hardware Security Byte (see &quo

37T89C51154128A–8051–04/02Registers FCON RegisterFCON (S:D1h)Flash Control RegisterReset Value = 0000 0000b76543210FPL3 FPL2 FPL1 FPL0 FPS FMOD1 FMOD0

38T89C51154128A–8051–04/02In-SystemProgramming (ISP)With the implementation of the User Space (FM0) and the Boot Space (FM1) in Flashtechnology the T8

39T89C51154128A–8051–04/02Boot ProcessSoftware Boot ProcessExampleMany algorithms can be used for the software boot process. Before describing them,Th

4T89C51154128A–8051–04/02Table 1. Pin DescriptionPin Name Type DescriptionVSS GND Circuit groundVCC Supply VoltageVAREF Reference Voltage for ADCVAVCC

40T89C51154128A–8051–04/02ApplicationProgramming InterfaceSeveral Application Program Interface (API) calls are available for use by an applicationpro

41T89C51154128A–8051–04/02Hardware Security Byte Table 25. Hardware Security byteDefault value after erasing chip: FFhNotes: 1. Only the 4 MSB bits ca

42T89C51154128A–8051–04/02Serial I/O Port The T89C5115 I/O serial port is compatible with the I/O serial port in the 80C52.It provides both synchronou

43T89C51154128A–8051–04/02valid stop bits cannot clear the FE bit. When the FE feature is enabled, RI rises on thestop bit instead of the last data bi

44T89C51154128A–8051–04/02Given Address Each device has an individual address that is specified in the SADDR register; theSADEN register is a mask byt

45T89C51154128A–8051–04/02For slaves A and B, bit 2 is a don’t care bit; for slave C, bit 2 is set. To communicate withall of the slaves, the master m

46T89C51154128A–8051–04/02Table 27. SADEN RegisterSADEN (S:B9h)Slave Address Mask RegisterReset Value = 0000 0000bNot bit addressableTable 28. SADDR R

47T89C51154128A–8051–04/02Table 30. PCON RegisterPCON (S:87h)Power Control RegisterReset Value = 00x1 0000bNot bit addressable76543210SMOD1 SMOD0 - PO

48T89C51154128A–8051–04/02Timers/Counters The T89C5115 implements two general-purpose, 16-bit Timers/Counters. Such areidentified as Timer 0 and Timer

49T89C51154128A–8051–04/02Mode 0 (13-bit Timer) Mode 0 configures Timer 0 as an 13-bit Timer which is set up as an 8-bit Timer (TH0register) with a mo

5T89C51154128A–8051–04/02P3.0:7 I/O Port 3:Is an 8-bit bi-directional I/O port with internal pull-ups. Port 3 pins that have 1’swritten to them are pu

50T89C51154128A–8051–04/02Mode 2 (8-bit Timer with Auto-Reload)Mode 2 configures Timer 0 as an 8-bit Timer (TL0 register) that automatically reloadsfr

51T89C51154128A–8051–04/02Timer 1 Timer 1 is identical to Timer 0 excepted for Mode 3 which is a hold-count mode. Follow-ing comments help to understa

52T89C51154128A–8051–04/02Interrupt Each Timer handles one interrupt source that is the timer overflow flag TF0 or TF1. Thisflag is set every time an

53T89C51154128A–8051–04/02Registers Table 31. TCON RegisterTCON (S:88h)Timer/Counter Control RegisterReset Value = 0000 0000b76543210TF1 TR1 TF0 TR0 I

54T89C51154128A–8051–04/02Table 32. TMOD RegisterTMOD (S:89h)Timer/Counter Mode Control RegisterNotes: 1. Reloaded from TH1 at overflow.2. Reloaded fr

55T89C51154128A–8051–04/02Table 33. TH0 RegisterTH0 (S:8Ch)Timer 0 High Byte RegisterReset Value = 0000 0000bTable 34. TL0 RegisterTL0 (S:8Ah)Timer 0

56T89C51154128A–8051–04/02Table 36. TL1 RegisterTL1 (S:8Bh)Timer 1 Low Byte RegisterReset Value = 0000 0000b76543210BitNumberBitMnemonic Description7:

57T89C51154128A–8051–04/02Timer 2 The T89C5115 Timer 2 is compatible with Timer 2 in the 80C52.It is a 16-bit timer/counter: the count is maintained b

58T89C51154128A–8051–04/02Programmable Clock-OutputIn clock-out mode, Timer 2 operates as a 50%-duty-cycle, programmable clock genera-tor (See Figure

59T89C51154128A–8051–04/02Registers Table 37. T2CON RegisterT2CON (S:C8h)Timer 2 Control RegisterReset Value = 0000 0000bBit addressable76543210TF2 EX

6T89C51154128A–8051–04/02I/O Configurations Each Port SFR operates via type-D latches, as illustrated in Figure 1 for Ports 3 and 4. ACPU "write

60T89C51154128A–8051–04/02Table 38. T2MOD RegisterT2MOD (S:C9h)Timer 2 Mode Control RegisterReset Value = XXXX XX00bNot bit addressableTable 39. TH2 R

61T89C51154128A–8051–04/02Table 40. TL2 RegisterTL2 (S:CCh)Timer 2 Low Byte RegisterReset Value = 0000 0000bNot bit addressableTable 41. RCAP2H Regist

62T89C51154128A–8051–04/02WatchDog Timer T89C5115 contains a powerful programmable hardware WatchDog Timer (WDT) thatautomatically resets the chip if

63T89C51154128A–8051–04/02WatchDog Programming The three lower bits (S0, S1, S2) located into WDTPRG register permit to program theWDT duration.Table

64T89C51154128A–8051–04/02WatchDog Timerduring Power-downMode and IdleIn Power-down mode the oscillator stops, which means the WDT also stops. While i

65T89C51154128A–8051–04/02Table 46. WDTRST RegisterWDTRST (S:A6h Write only)WatchDog Timer Enable RegisterReset Value = 1111 1111bNote: The WDRST regi

66T89C51154128A–8051–04/02ProgrammableCounter Array (PCA)The PCA provides more timing capabilities with less CPU intervention than the standardtimer/c

67T89C51154128A–8051–04/02Figure 30. PCA Timer/CounterThe CMOD register includes three additional bits associated with the PCA.• The CIDL bit which al

68T89C51154128A–8051–04/02PCA Modules Each one of the five compare/capture modules has six possible functions. It canperform:• 16-bit Capture, positiv

69T89C51154128A–8051–04/02PCA InterruptFigure 31. PCA Interrupt SystemPCA Capture Mode To use one of the PCA modules in capture mode either one or bot

7T89C51154128A–8051–04/02Read-Modify-WriteInstructionsSome instructions read the latch data rather than the pin data. The latch based instruc-tions re

70T89C51154128A–8051–04/0216-bit Software TimerModeThe PCA modules can be used as software timers by setting both the ECOM and MATbits in the modules

71T89C51154128A–8051–04/02High Speed Output Mode In this mode the CEX output (on port 1) associated with the PCA module will toggleeach time a match o

72T89C51154128A–8051–04/02Figure 35. PCA PWM ModeCL rolls over from FFh TO 00h loadsCCAPnH contents into CCAPnLCCAPnLCCAPnH8-BitComparatorCL (8 bits)“

73T89C51154128A–8051–04/02PCA Registers Table 47. CMOD RegisterCMOD (S:D9h)PCA Counter Mode RegisterReset Value = 00XX X000b76543210CIDL WDTE - - - CP

74T89C51154128A–8051–04/02Table 48. CCON RegisterCCON (S:D8h)PCA Counter Control RegisterReset Value = 00xx xx00b76543210CF CR - - - - CCF1 CCF0BitNum

75T89C51154128A–8051–04/02Table 49. CCAPnH RegistersCCAP0H (S:FAh)CCAP1H (S:FBh)PCA High Byte Compare/Capture Module n Register (n=0..1)Reset Value =

76T89C51154128A–8051–04/02Table 51. CCAPMn RegistersCCAPM0 (S:DAh)CCAPM1 (S:DBh)PCA Compare/Capture Module n Mode registers (n=0..1)Reset Value = X000

77T89C51154128A–8051–04/02Table 52. CH RegisterCH (S:F9h)PCA Counter Register High ValueReset Value = 0000 00000bTable 53. CL RegisterCL (S:E9h)PCA co

78T89C51154128A–8051–04/02Analog-to-DigitalConverter (ADC)This section describes the on-chip 10-bit analog-to-digital converter of the T89C5115.Eight

79T89C51154128A–8051–04/02Figure 36. ADC DescriptionFigure 37 shows the timing diagram of a complete conversion. For simplicity, the figuredepicts the

8T89C51154128A–8051–04/02associated nFET is switched off. This is traditional CMOS switch convention. Currentstrengths are 1/10 that of pFET #3Figure

80T89C51154128A–8051–04/02Table 54. Selected Analog InputVoltage Conversion When the ADCIN is equals to VAREF the ADC converts the signal to 3FFh (ful

81T89C51154128A–8051–04/02IT ADC Management An interrupt end-of-conversion will occurs when the bit ADEOC is activated and the bitEADC is set. For re-

82T89C51154128A–8051–04/02Registers Table 55. ADCF RegisterADCF (S:F6h)ADC ConfigurationReset Value = 0000 0000bTable 56. ADCON RegisterADCON (S:F3h)A

83T89C51154128A–8051–04/02Table 57. ADCLK RegisterADCLK (S:F2h)ADC Clock PrescalerReset Value = XXX0 0000bTable 58. ADDH RegisterADDH (S:F5h Read Only

84T89C51154128A–8051–04/02Interrupt SystemIntroduction The T89C5115 has a total of 8 interrupt vectors: two external interrupts (INT0 andINT1), three

85T89C51154128A–8051–04/02Table 60. Priority Level Bit ValuesA low-priority interrupt can be interrupted by a high priority interrupt but not by anoth

86T89C51154128A–8051–04/02Registers Table 62. IEN0 RegisterIEN0 (S:A8h)Interrupt Enable RegisterReset Value = 0000 0000bbit addressable76543210EA EC E

87T89C51154128A–8051–04/02Table 63. IEN1 RegisterIEN1 (S:E8h)Interrupt Enable RegisterReset Value = xxxx xx0xbbit addressable76543210------EADC-BitNum

88T89C51154128A–8051–04/02Table 64. IPL0 RegisterIPL0 (S:B8h)Interrupt Enable RegisterReset Value = X000 0000bbit addressable76543210- PPC PT2 PS PT1

89T89C51154128A–8051–04/02Table 65. IPL1 RegisterIPL1 (S:F8h)Interrupt Priority Low Register 1Reset Value = xxxx xx0xbbit addressable76543210- - - - -

9T89C51154128A–8051–04/02SFR Mapping The Special Function Registers (SFRs) of the T89C5115 fall into the followingcategories:Table 3. C51CoreSFRsMnemo

90T89C51154128A–8051–04/02Table 66. IPL0 RegisterIPH0 (B7h)Interrupt High Priority RegisterReset Value = X000 0000b76543210- PPCH PT2H PSH PT1H PX1H P

91T89C51154128A–8051–04/02Table 67. IPH1 RegisterIPH1 (S:F7h)Interrupt high priority Register 1Reset Value = xxxx xx0xb76543210- - - - - - PADCH -BitN

92T89C51154128A–8051–04/02Electrical CharacteristicsAbsolute Maximum RatingsDC Parameters for Standard VoltageTA =-40°Cto+85°C; VSS=0V; VCC=5V± 10%; F

93T89C51154128A–8051–04/025. Under steady state (non-transient) conditions, IOLmust be externally limited as fol-lows:Maximum IOLper port pin: 10 mAMa

94T89C51154128A–8051–04/02Figure 44. Clock Signal Waveform for ICCTests in Active and Idle ModesDC Parameters for A/DConverterTable 69. DC Parameters

95T89C51154128A–8051–04/02AC ParametersExplanation of the ACSymbolsEach timing symbol has 5 characters. The first character is always a “T” (stands fo

96T89C51154128A–8051–04/02Table 72. AC Parameters for a Variable ClockShift Register Timing WaveformsExternal Clock DriveCharacteristics (XTAL1)Table

97T89C51154128A–8051–04/02Float WaveformsFor timing purposes as port pin is no longer floating when a 100 mV change from loadvoltage occurs and begins

98T89C51154128A–8051–04/02Ordering InformationTable 75. Possible Order EntriesPart-NumberMemory Size Supply VoltageTemperatureRangeMaxFrequency Packag

99T89C51154128A–8051–04/02Package DrawingPLCC28