
MAX5480
8-Bit Parallel DAC in
QSOP-16 Package
_______________________________________________________________________________________ 5
INTERFACE LOGIC
S7 S6
S1
20kΩ 20kΩ 20kΩ 20kΩ
10kΩ
S8
D6 D5
D0 (LSB)
D7 (MSB)
20kΩ
10kΩ
REF
10kΩ
10kΩ
OUT2
CS
OUT1
RFB
WR
Figure 3. MAX5480 Functional Diagram
t
CH
t
CS
0
V
DD
0
V
DD
0
NOTES:
1. FOR THE MAX5480, ALL INPUT SIGNAL RISE AND FALL TIMES ARE MEASURED
FROM 10% TO 90% OF V
DD
. V
DD
= +5V, t
r
= t
f
= 20ns.
2. TIMING MEASUREMENT REFERENCE LEVEL IS (V
IH
+ V
IL
) / 2.
CS
WR
DATA IN
(D7–D0)
DATA IN
STABLE
V
DD
t
WR
t
DS
V
IH
V
IL
t
DH
Figure 4. Write-Cycle Timing Diagram
Table 2. Unipolar Binary Code Table Table 3. Bipolar (Offset Binary) Code Table
NOTE LSB V V
REF REF
: 1 2
1
256
8
=
( )
=
( )
−
NOTE LSB V V
REF REF
: 1 2
1
128
7
=
( )
=
( )
−
DIGITAL INPUT
MSB LSB
1 1 1 1 1 1 1 1
1 0 0 0 0 0 0 1
ANALOG OUTPUT
1 0 0 0 0 0 0 0
0 1 1 1 1 1 1 1
0 0 0 0 0 0 0 1
0 0 0 0 0 0 0 0
DIGITAL INPUT
MSB LSB
1 1 1 1 1 1 1 1
1 0 0 0 0 0 0 1
ANALOG OUTPUT
1 0 0 0 0 0 0 0
0 1 1 1 1 1 1 1
0 0 0 0 0 0 0 1
0 0 0 0 0 0 0 0
-V
255
256
REF
-V
129
256
REF
-V
128
256
REF
= −
V
REF
2
-V
127
256
REF
-V
1
256
REF
-V
0
256
REF
= 0
+V
127
128
REF
+V
1
128
REF
-V
1
128
REF
-V
127
128
REF
-V
128
128
REF
Comentários a estes Manuais