MAX5158/MAX5159
Low-Power, Dual, 10-Bit, Voltage-Output DACs
with Serial Interface
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ELECTRICAL CHARACTERISTICS—MAX5158 (continued)
(V
DD
= +5V ±10%, V
REFA
= V
REFB
= 2.048V, R
L
= 10kΩ, C
L
= 100pF, T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are
at T
A
= +25°C (OS_ tied to AGND for a gain of +2V/V).)
Note 1: Accuracy is specified from code 2 to code 1023.
Note 2: Accuracy is better than 1LSB for V
OUT
_ greater than 6mV and less than V
DD
- 50mV. Guaranteed by PSRR test at the
end points.
Note 3: Digital inputs are set to either V
DD
or DGND, code = 0000 hex, R
L
= ∞.
Note 4: SCLK minimum clock period includes rise and fall times.
CS = V
DD
, f
DIN
= 100kHz, V
SCLK
= 5Vp-p
I
SOURCE
= 2mA
(Note 4)
(Note 3)
(Note 3)
ns
Rail-to-rail (Note 2)
To 1/2LSB of full-scale, V
STEP
= 4V
40
I
SINK
= 2mA
t
CL
SCLK Pulse Width Low
CONDITIONS
ns40t
CH
SCLK Pulse Width High
nV-s5Digital Crosstalk
nV-s5Digital Feedthrough
µs25Time Required to Exit Shutdown
kΩ24 34R
OS_
OSA or OSB Input Resistance
ns100t
CP
SCLK Clock Period
µA0 ±1Reference Current in Shutdown
µA2 10I
DD(SHDN)
Power-Supply Current
in Shutdown
mA0.5 0.65I
DD
Power-Supply Current
V4.5 5.5V
DD
Positive Supply Voltage
ns40t
DS
SDI Setup Time
ns
VV
DD
- 0.5V
OH
Output High Voltage
0t
CSH
SCLK Rise to CS Rise Hold Time
ns40t
CSS
CS Fall to SCLK Rise Setup Time
C
LOAD
= 200pF
V0 to V
DD
Output Voltage Swing
µs8Output Settling Time
C
LOAD
= 200pF
ns80
V0.13 0.4V
OL
Output Low Voltage
V/µs0.75SRVoltage Output Slew Rate
UNITSMIN TYP MAXSYMBOLPARAMETER
t
DO2
SCLK Fall to DOUT
Valid Propagation Delay
ns80t
DO1
SCLK Rise to DOUT
Valid Propagation Delay
ns0t
DH
SDI Hold Time
ns100t
CSW
CS Pulse Width High
ns40t
CS1
CS Rise to SCLK Rise Hold
ns10t
CS0
SCLK Rise to CS Fall Delay
DIGITAL OUTPUTS (DOUT, UPO)
DYNAMIC PERFORMANCE
POWER SUPPLIES
TIMING CHARACTERISTICS
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