Rainbow-electronics MAX19516 Manual do Utilizador descarregar pdf (Página 4)

MAX19516

Dual-Channel, 10-Bit, 100Msps ADC

4 _______________________________________________________________________________________

ELECTRICAL CHARACTERISTICS (continued)

AVDD

= V

OVDD

= 1.8V, internal reference, differential clock, V

CLK

= 1.5V

P-P

, f

CLK

= 100MHz, A

= -0.5dBFS, data output termina-

tion = 50Ω, T

= -40°C to +85°C, unless otherwise noted. Typical values are at T

= +25°C.) (Note 1)

PARAMETER

SYMBOL

CONDITIONS

MIN TYP MAX

UNITS

INTERCHANNEL CHARACTERISTICS

INA

or f

INB

= 70MHz at -1dBFS 95

Crosstalk

INA

or f

INB

= 175MHz at -1dBFS 85

dBc

Gain Match f

= 70MHz

±0.05

Offset Match f

= 70MHz

±0.1

%FSR

Phase Match f

= 70MHz

±0.5

D eg r ees

ANALOG OUTPUTS (CMA, CMB)

CMA, CMB Output Voltage V

COM

Default programmable setting

0.85

0.9

0.95

INTERNAL REFERENCE

REFIO Output Voltage

REFOUT

1.23 1.25 1.27

REFIO Temperature Coefficient TC

REF

< ±60

ppm/°C

EXTERNAL REFERENCE

REFIO Input-Voltage Range V

REFIN

1.25 +5/

-10%

REFIO Input Resistance R

REFIN

±20%

kΩ

CLOCK INPUTS (CLK+, CLK-)—DIFFERENTIAL MODE

Differential Clock Input Voltage

0.4 to 2.0

P-P

Self-biased 1.2

Differential Input Common-Mode

Voltage

DC-coupled clock signal

1.0 to 1.4

Differential, default 10 kΩ

Differential, internal termination selected

100

ΩInput Resistance R

CLK

Common mode 9 kΩ

Input Capacitance C

CLK

To ground, each input 3 pF

CLOCK INPUTS (CLK+, CLK-)—SINGLE-ENDED MODE (V

CLK-

< 0.1V)

Single-Ended Mode Selection

Threshold (V

CLK-

)

0.1 V

Allowable Logic Swing (V

CLK+

)

0 - V

AVDD

Single-Ended Clock Input High

Threshold (V

CLK+

)

1.5 V

Single-Ended Clock Input Low

Threshold (V

CLK+

)

0.3 V

CLK+

= V

AVDD

= 1.8V or 3.3V

+0.5

Input Leakage (CLK+)

CLK+

= 0

-0.5

µA

Input Leakage (CLK-) V

CLK-

= 0

-150

-50 µA

Input Capacitance (CLK+) 3pF

1 2 3 4 5 6 7 8 9 ... 33 34

MAX19516 1

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