Rainbow-electronics MAX1126 Manual do Utilizador descarregar pdf (Página 19)

MAX1126

Quad, 12-Bit, 40Msps, 1.8V ADC with

Serial LVDS Outputs

______________________________________________________________________________________ 19

System Timing Requirements

Figure 3 shows the relationship between the analog

inputs, input clock, frame alignment output, serial clock

output, and serial data output. The differential analog

input (IN_P and IN_N) is sampled on the rising edge of

the CLK signal and the resulting data appears at the

digital outputs 6.5 clock cycles later. Figure 4 provides

a detailed, two-conversion timing diagram of the rela-

tionship between the inputs and the outputs.

Clock Output (CLKOUTP, CLKOUTN)

The MAX1126 provides a differential clock output that

consists of CLKOUTP and CLKOUTN. As shown in

Figure 4, the serial output data is clocked out of the

MAX1126 on both edges of the clock output. The fre-

quency of the output clock is 6 times the frequency

of CLK.

OUTPUT

DATA FOR

SAMPLE

N - 6

OUTPUT

DATA FOR

SAMPLE N

*DUTY CYCLE VARIES DEPENDING ON INPUT CLOCK FREQUENCY.

CLK

N + 2

N + 1

N + 3

N + 4

N + 5

N + 6

N + 7

N + 8

N + 9

6.5 CLOCK-CYCLE DATA LATENCY

SAMPLE

IN_P

IN_N

)

FRAMEP

FRAMEN

CLKOUTP

CLKOUTN

)

OUT_P

OUT_N

)

Figure 3. Global Timing Diagram

N + 2

N + 1

*DUTY CYCLE DEPENDS ON INPUT CLOCK FREQUENCY.

IN_P

- V

IN_N

)

CLK

FRAMEP

FRAMEN

)

CLKOUTP

CLKOUTN

)

OUT_P

OUT_N

)

N-7

D10

N-7

D11

N-7

N-6

D10

N-6

D11

N-6

N-5

SAMPLE

Figure 4. Detailed Two-Conversion Timing Diagram

1 2 ... 14 15 16 17 18 19 20 21 22 23 24 25

Serial LVDS Outputs 1

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