
MAX1091/MAX1093
250ksps, +3V, 8-/4-Channel, 10-Bit ADCs
with +2.5V Reference and Parallel Interface
14 ______________________________________________________________________________________
Table 3. Channel Selection for Single-Ended Operation (SGL/DIF = 1)
*Channels CH4–CH7 apply to MAX1091 only.
A1 CH0
0 +00
A0
0 1
CH2 CH4*
+0
1 0 +
CH3
-
0
CH1 CH7*
-
CH6*
-
COM
1
CH5*
1 + -0
0 0
A2
+1
0 1 +1
-
-
1 01
1 1
+
1
-
+ -
WR
CLK
CLK
WR
WR GOES HIGH WHEN CLK IS HIGH.
WR GOES HIGH WHEN CLK IS LOW.
t
DH
t
DH
t
CWH
t
CWS
ACQUISITION STARTS
ACQUISITION STARTS
CONVERSION STARTS
CONVERSION STARTS
ACQUISITION ENDS
ACQUISITION ENDS
ACQMOD = "1"
ACQMOD = "1"
ACQMOD = "0"
ACQMOD = "0"
Figure 6b. External Clock and
WR
Timing (External Acquisition Mode)
Table 2. Control Byte Format
D7 (MSB) D3 D1 D0 (LSB)D2D5
PD1
UNI/BIP
A1 A0A2ACQMOD
SGL/DIF
PD0
D4D6
Comentários a estes Manuais