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ATtiny28L/V

1062E–10/01

• Bit 2 – RES: Reserved Bit

This bit is a reserved bit in the ATtiny28 and will always read as zero.

• Bits 1, 0 - ACIS1, ACIS0: Analog Comparator Interrupt Mode Select

These bits determine which comparator events trigger the Analog Comparator Interrupt.

The different settings are shown in Table 16.

Note: When changing the ACIS1/ACIS0 bits, the Analog Comparator Interrupt must be dis-

abled by clearing its Interrupt Enable bit in the ACSR register. Otherwise, an interrupt can

occur when the bits are changed.

Caution: Using the SBI or CBI instruction on bits other than ACI in this register will write

a one back into ACI if it is read as set, thus clearing the flag.

Table 16. ACIS1/ACIS0 Settings

ACIS1 ACIS0 Interrupt Mode

0 0 Comparator Interrupt on Output Toggle

01Reserved

1 0 Comparator Interrupt on Falling Output Edge

1 1 Comparator Interrupt on Rising Output Edge

1 2 ... 30 31 32 33 34 35 36 37 38 39 40 ... 74 75

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