Rainbow-electronics AT90C8534 Manual do Utilizador descarregar pdf (Página 15)

AT90C8534

Figure 21 shows the internal timing concept for the register file. In a single clock cycle an ALU operation using two register

operands is executed and the result is stored back to the destination register.

Figure 21. Single Cycle ALU Operation

The internal data SRAM access is performed in two System Clock cycles as described in Figure 22.

Figure 22. On-Chip Data SRAM Access Cycles

System Clock Ø

Total Execution Time

ALU Operation Execute

Result Write Back

T1 T2 T3 T4

System Clock Ø

Data

Address

T1 T2 T3 T4

Prev. Address

Read

Write

1 2 ... 10 11 12 13 14 15 16 17 18 19 20 ... 53 54

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