AC Electrical Characteristics
The following specifications apply for DV
CC
e
AV
CC
ea
5.0V, V
b
eb
5.0V, t
r
e
t
f
e
20 ns unless otherwise specified.
Boldface limits apply for T
A
e
T
J
e
T
MIN
to T
MAX
; all other limits T
A
e
T
J
e
25
§
C. (Notes 6 and 7)
Symbol Parameter Conditions
Typical Limit Units
(Note 9) (Notes 10, 18) (Limits)
f
CLK
Clock Frequency 2.0 MHz
0.5 MHz(min)
4.0 MHZ(max)
Clock Duty Cycle 50 %
40 %(min)
60 %(max)
t
C
Conversion Time 27(1/f
CLK
) 27(1/f
CLK
)
a
300 ns (max)
f
CLK
e
2.0 MHz 13.5 ms
t
A
Acquisition Time R
SOURCE
e
50X 7(1/f
CLK
) 7(1/f
CLK
)
a
300 ns (max)
(Note 15) f
CLK
e
2.0 MHz 3.5 ms
t
Z
Auto Zero Time 26 26 1/f
CLK
(max)
f
CLK
e
2.0 MHz 13 ms
t
CAL
Calibration Time 1396 1/f
CLK
f
CLK
e
2.0 MHz 698 706 ms (max)
t
W(CAL)L
Calibration Pulse Width (Note 16) 60 200 ns(min)
t
W(WR)L
Minimum WR Pulse Width 60 200 ns(min)
t
ACC
Maximum Access Time C
L
e
100 pF
(Delay from Falling Edge of 50 85 ns(max)
RD
to Output Data Valid)
t
0H
,t
1H
TRI-STATE Control (Delay R
L
e
1kX,
from Rising Edge of RD
C
L
e
100 pF 30 90 ns(max)
to Hi-Z State)
t
PD(INT)
Maximum Delay from Falling Edge of
100 175 ns(max)
RD
or WR to Reset of INT
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed
specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test
conditions.
Note 2: All voltages are measured with respect to AGND and DGND, unless otherwise specified.
Note 3: When the input voltage (V
IN
) at any pin exceeds the power supply rails (V
IN
k
V
b
or V
IN
l
(AV
CC
or DV
CC
), the current at that pin should be limited to
5 mA. The 20 mA maximum package input current rating allows the voltage at any four pins, with an input current limit of 5 mA, to simultaneously exceed the power
supply voltages.
Note 4: The maximum power dissipation must be derated at elevated temperatures and is dictated by T
JMAX
(maximum junction temperature), i
JA
(package
junction to ambient thermal resistance), and T
A
(ambient temperature). The maximum allowable power dissipation at any temperature is P
Dmax
e
(T
Jmax
b
T
A
)/i
JA
or the number given in the Absolute Maximum Ratings, whichever is lower. For this device, T
Jmax
e
125
§
C, and the typical thermal resistance (i
JA
)ofthe
ADC1241 with CMJ, BIJ, and CIJ suffixes when board mounted is 47
§
C/W.
Note 5: Human body model, 100 pF discharged through a 1.5 kX resistor.
Note 6: Two on-chip diodes are tied to the analog input as shown below. Errors in the A/D conversion can occur if these diodes are forward biased more than
50 mV.
TL/H/10554–3
This means that if AV
CC
and DV
CC
are minimum (4.75 V
DC
) and V
b
is maximum (
b
4.75 V
DC
), full-scale must be
s
4.8 V
DC
.
4
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