Rainbow-electronics ADC12041 Manual do Utilizador Página 20
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Pin Description
PLCC and
Pin
SSOP Pkg.
Name
Description
Pin Number
5V
IN
a
The analog ADC inputs. V
IN
a
is the non-inverting (positive) input and V
IN
b
is the inverting (negative)
6V
IN
b
input into the ADC.
10 V
REF
a
Positive reference input. The operating voltage range for this input is 1V
s
V
REF
a
s
V
A
a
(see
Figures
3
and
4
). This pin should be bypassed to AGND at least with a parallel combination of a 10 mF and a
0.1 mF (ceramic) capacitor. The capacitors should be placed as close to the part as possible.
9V
REF
b
Negative reference input. The operating voltage range for this input is 0V
s
V
REF
b
s
V
REF
a
b
1 (see
Figures 3
and
4
). This pin should be bypassed to AGND at least with a parallel combination of a 10 mF
and a 0.1 mF (ceramic) capacitor. The capacitors should be placed as close to the part as possible.
4 WMODE The logic state of this pin at power-up determines which edge of the write signal (WR) will latch in data
from the data bus. If tied low, the ADC12041 will latch in data on the rising edge of the WR
signal. If tied
to a logic high, data will be latched in on the falling edge of the WR
signal. The state of this pin should
not be changed after power-up.
27 SYNC The SYNC pin can be programmed as an input or an output. The Configuration register’s bit b4 controls
the function of this pin. When programmed as an input pin (b4
e
1), a rising edge on this pin causes the
ADC’s sample-and-hold to hold the analog input signal and begin conversion. When programmed as an
output pin (b4
e
0), the SYNC pin goes high when a conversion begins and returns low when
completed.
12– 20 D0– D8 13-bit Data bus of the ADC12041. D12 is the most significant bit and D0 is the least significant. The
23– 26 D9– D12 BW(bus width) bit of the Configuration register (b3) selects between an 8-bit or 13-bit data bus width.
When the BW bit is cleared (BW
e
0), D7– D0 are active and D12–D8 are always in TRI-STATE
É
.
When the BW bit is set (BW
e
1), D12– D0 are active.
28 CLK The clock input pin used to drive the ADC12041. The operating range is 0.05 MHz to 12 MHz.
1WRWR is the active low WRITE control input pin. A logic low on this pin and the CS will enable the input
buffers of the data pins D12– D0. The signal at this pin is used by the ADC12041 to latch in data on
D12– D0. The sense of the WMODE pin at power-up will determine which edge of the WR
signal the
ADC12041 will latch in data. See WMODE pin description.
2RDRD is the active low read control input pin. A logic low on this pin and CS will enable the active output
buffers to drive the data bus.
3CSCS is the active low Chip Select input pin. Used in conjunction with the WR and RD signals to control the
active data bus input/output buffers of the data bus.
11 RDY RDY is an active low output pin. The signal at this pin indicates when a requested function has begun or
ended. Refer to section Functional Description and the digital timing diagrams for more detail.
7V
A
a
Analog supply input pin. The device operating supply voltage range is
a
5V
g
10%. Accuracy is
guaranteed only if the V
A
a
and V
D
a
are connected to the same potential. This pin should be bypassed
to AGND with a parallel combination of a 10 mF and a 0.1 mF (ceramic) capacitor. The capacitors should
be placed as close to the supply pins of the part as possible.
8 AGND Analog ground pin. This is the device’s analog supply ground connection. It should be connected
through a low resistance and low inductance ground return to the system power supply.
21 V
D
a
Digital supply input pins. The device operating supply voltage range is
a
5V
g
10%. Accuracy is
guaranteed only if the V
A
a
and V
D
a
are connected to the same potential. This pin should be bypassed
to DGND with a parallel combination of a 10 mF and a 0.1 mF (ceramic) capacitor. The capacitors should
be placed as close to the supply pins of the part as possible.
22 DGND Digital ground pin. This is the device’s digital supply ground connection. It should be connected through
a low resistance and low inductance ground return to the system power supply.
28-Pin SSOP
TL/H/12441–2
28-Pin PLCC
TL/H/12441–3
20
- ADC12041 1
- Analog-to-Digital Converter 1
- Connection Diagrams 2
- Ordering Information 2
- Absolute Maximum Ratings 3
- Notes on Specifications 6
- Figure 6 7
- Electrical Characteristics 8
- TL/H/12441–7 9
- TL/H/12441–8 9
- (Continued) 10
- Timing Diagrams 12
- Timing Diagrams (Continued) 13
- TL/H/12441–29 18
- TL/H/12441–30 18
- TL/H/12441–31 18
- TL/H/12441–32 18
- Pin Description 20
- Register Bit Description 21
- Functional Description 22
- Features and Operating Modes 22
- 8-bit mode: 23
- 13-bit mode: 23
- SYNC-OUT/Asynchronous 23
- SYNC-IN/Synchronous 24
- Figure 8 25
- Figure 9 25
- Figure 10 26
- Order Number ADC12041CIV 29
- NS Package Number V28A 29
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