Rainbow-electronics ADC0820 Manual do Utilizador Página 7
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Description of Pin Functions
Pin Name Function
1V
IN
Analog input; range
e
GND
s
V
IN
s
V
CC
2 DB0 TRI-STATE data outputÐbit 0 (LSB)
3 DB1 TRI-STATE data outputÐbit 1
4 DB2 TRI-STATE data outputÐbit 2
5 DB3 TRI-STATE data outputÐbit 3
6WR
/RDY WR-RD Mode
WR
: With CS low, the conversion is start-
ed on the falling edge of WR
. Approxi-
mately 800 ns (the preset internal time
out, t
I
) after the WR rising edge, the result
of the conversion will be strobed into the
output latch, provided that RD
does not
occur prior to this time out (see
Figures
3a
and
3b
).
RD Mode
RDY: This is an open drain output (no in-
ternal pull-up device). RDY will go low af-
ter the falling edge of CS
; RDY will go
TRI-STATE when the result of the conver-
sion is strobed into the output latch. It is
used to simplify the interface to a micro-
processor system (see
Figure 2
).
7 Mode Mode: Mode selection inputÐit is inter-
nally tied to GND through a 50 mA current
source.
RD Mode: When mode is low
WR-RD Mode: When mode is high
8RD
WR-RD Mode
With CS
low, the TRI-STATE data outputs
(DB0-DB7) will be activated when RD
goes low (see
Figure 4
). RD can also be
used to increase the speed of the con-
verter by reading data prior to the preset
internal time out (t
I
,
E
800 ns). If this is
done, the data result transferred to output
latch is latched after the falling edge of
the RD
(see
Figures 3a
and
3b
).
RD Mode
With CS
low, the conversion will start with
RD
going low, also RD will enable the
TRI-STATE data outputs at the comple-
tion of the conversion. RDY going TRI-
STATE and INT
going low indicates the
completion of the conversion (see
Figure
2
).
Pin Name Function
9 INT WR-RD Mode
INT
going low indicates that the conver-
sion is completed and the data result is in
the output latch. INT
will go low,
E
800 ns
(the preset internal time out, t
I
) after the
rising edge of WR
(see
Figure 3b
); or INT
will go low after the falling edge of RD,if
RD
goes low prior to the 800 ns time out
(see
Figure 3a
). INT is reset by the rising
edge of RD
or CS (see
Figures 3a
and
3b
).
RD Mode
INT
going low indicates that the conver-
sion is completed and the data result is in
the output latch. INT
is reset by the rising
edge of RD
or CS (see
Figure 2
).
10 GND Ground
11 V
REF
(
b
) The bottom of resistor ladder, voltage
range: GND
s
V
REF
(
b
)
s
V
REF
(
a
) (Note
5)
12 V
REF
(
a
) The top of resistor ladder, voltage range:
V
REF
(
b
)
s
V
REF
(
a
)
s
V
CC
(Note 5)
13 CS
CS must be low in order for the RD or WR
to be recognized by the converter.
14 DB4 TRI-STATE data outputÐbit 4
15 DB5 TRI-STATE data outputÐbit 5
16 DB6 TRI-STATE data outputÐbit 6
17 DB7 TRI-STATE data outputÐbit 7 (MSB)
18 OFL
Overflow outputÐIf the analog input is
higher than the V
REF
(
a
), OFL will be low
at the end of conversion. It can be used to
cascade 2 or more devices to have more
resolution (9, 10-bit). This output is always
active and does not go into TRI-STATE
as DB0 – DB7 do.
19 NC No connection
20 V
CC
Power supply voltage
1.0 Functional Description
1.1 GENERAL OPERATION
The ADC0820 uses two 4-bit flash A/D converters to make
an 8-bit measurement (
Figure 1
). Each flash ADC is made
up of 15 comparators which compare the unknown input to
a reference ladder to get a 4-bit result. To take a full 8-bit
reading, one flash conversion is done to provide the 4 most
significant data bits (via the MS flash ADC). Driven by the 4
MSBs, an internal DAC recreates an analog approximation
of the input voltage. This analog signal is then subtracted
from the input, and the difference voltage is converted by a
second 4-bit flash ADC (the LS ADC), providing the 4 least
significant bits of the output data word.
The internal DAC is actually a subsection of the MS flash
converter. This is accomplished by using the same resistor
ladder for the A/D as well as for generating the DAC signal.
The DAC output is actually the tap on the resistor ladder
which most closely approximates the analog input. In addi-
tion, the ‘’sampled-data’’ comparators used in the ADC0820
provide the ability to compare the magnitudes of several
analog signals simultaneously, without using input summing
amplifiers. This is especially useful in the LS flash ADC,
where the signal to be converted is an analog difference.
7
- General Description 1
- Key Specifications 1
- Features 1
- TL/H/5501–3 4
- TL/H/5501–5 4
- TL/H/5501–4 4
- TL/H/5501–6 4
- Timing Diagrams 5
- TL/H/5501–11 6
- Description of Pin Functions 7
- 1.0 Functional Description 7
- TL/H/5501–12 8
- TL/H/5501–13 8
- TL/H/5501–14 8
- Detailed Block Diagram 9
- Figure 8 10
- Figure B 10
- 2.0 Analog Considerations 11
- TL/H/5501–24 12
- TL/H/5501–25 12
- TL/H/5501–21 12
- TL/H/5501–22 12
- TL/H/5501–23 12
- 3.0 Typical Applications 13
- (Continued) 14
- Fast Infinite Sample-and-Hold 14
- Digital Waveform Recorder 15
- Ordering Information 16
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