Rainbow-electronics ATtiny2313 Manual do Utilizador

1 2543A–AVR–08/03Features• Utilizes the AVR® RISC Architecture• AVR – High-performance and Low-power RISC Architecture– 120 Powerful Instructions – Mo

10ATtiny23132543A–AVR–08/03Instruction Execution TimingThis section describes the general access timing concepts for instruction execution. TheAVR CPU

100ATtiny23132543A–AVR–08/03The Timer/Counter Overflow Flag (TOV1) is set each time the counter reaches BOT-TOM. When either OCR1A or ICR1 is used for

101ATtiny23132543A–AVR–08/03Phase and Frequency Correct PWM ModeThe phase and frequency correct Pulse Width Modulation, or phase and frequency cor-rec

102ATtiny23132543A–AVR–08/03The Timer/Counter Overflow Flag (TOV1) is set at the same timer clock cycle as theOCR1x Registers are updated with the dou

103ATtiny23132543A–AVR–08/03Timer/Counter Timing DiagramsThe Timer/Counter is a synchronous design and the timer clock (clkT1) is thereforeshown as a

104ATtiny23132543A–AVR–08/03Figure 50. Timer/Counter Timing Diagram, no PrescalingFigure 51 shows the same timing data, but with the prescaler enable

105ATtiny23132543A–AVR–08/0316-bit Timer/Counter Register DescriptionTimer/Counter1 Control Register A – TCCR1A• Bit 7:6 – COM1A1:0: Compare Output Mo

106ATtiny23132543A–AVR–08/03Note: 1. A special case occurs when OCR1A/OCR1B equals TOP and COM1A1/COM1B1 isset. In this case the compare match is igno

107ATtiny23132543A–AVR–08/03Table 46 shows the COM1x1:0 bit functionality when the WGM13:0 bits are set to thephase correct or the phase and frequency

108ATtiny23132543A–AVR–08/03Note: 1. The CTC1 and PWM11:0 bit definition names are obsolete. Use the WGM12:0 definitions. However, the functionality a

109ATtiny23132543A–AVR–08/03(ICF1), and this can be used to cause an Input Capture Interrupt, if this interrupt isenabled.When the ICR1 is used as TOP

11ATtiny23132543A–AVR–08/03There are basically two types of interrupts. The first type is triggered by an event thatsets the interrupt flag. For these

110ATtiny23132543A–AVR–08/03A FOC1A/FOC1B strobe will not generate any interrupt nor will it clear the timer in ClearTimer on Compare match (CTC) mode

111ATtiny23132543A–AVR–08/03Input Capture Register 1 – ICR1H and ICR1LThe Input Capture is updated with the counter (TCNT1) value each time an event o

112ATtiny23132543A–AVR–08/03Timer/Counter Interrupt Flag Register – TIFR• Bit 7 – TOV1: Timer/Counter1, Overflow FlagThe setting of this flag is depen

113ATtiny23132543A–AVR–08/03USART The Universal Synchronous and Asynchronous serial Receiver and Transmitter(USART) is a highly flexible serial commun

114ATtiny23132543A–AVR–08/03The dashed boxes in the block diagram separate the three main parts of the USART(listed from the top): Clock Generator, Tr

115ATtiny23132543A–AVR–08/03Figure 53. Clock Generation Logic, Block DiagramSignal description:txclk Transmitter clock (Internal Signal).rxclk Receiv

116ATtiny23132543A–AVR–08/03Note: 1. The baud rate is defined to be the transfer rate in bit per second (bps)BAUD Baud rate (in bits per second, bps)f

117ATtiny23132543A–AVR–08/03Synchronous Clock Operation When synchronous mode is used (UMSEL = 1), the XCK pin will be used as either clockinput (Slav

118ATtiny23132543A–AVR–08/03Sp Stop bit, always high.IDLE No transfers on the communication line (RxD or TxD). An IDLE line must behigh.The frame form

119ATtiny23132543A–AVR–08/03The following simple USART initialization code examples show one assembly and oneC function that are equal in functionalit

12ATtiny23132543A–AVR–08/03When using the SEI instruction to enable interrupts, the instruction following SEI will beexecuted before any pending inter

120ATtiny23132543A–AVR–08/03Data Transmission – The USART TransmitterThe USART Transmitter is enabled by setting the Transmit Enable (TXEN) bit in the

121ATtiny23132543A–AVR–08/03Sending Frames with 9 Data BitIf 9-bit characters are used (UCSZ = 7), the ninth bit must be written to the TXB8 bit inUCS

122ATtiny23132543A–AVR–08/03Transmitter Flags and InterruptsThe USART Transmitter has two flags that indicate its state: USART Data RegisterEmpty (UDR

123ATtiny23132543A–AVR–08/03Data Reception – The USART ReceiverThe USART Receiver is enabled by writing the Receive Enable (RXEN) bit in theUCSRB Regi

124ATtiny23132543A–AVR–08/03Receiving Frames with 9 Data BitsIf 9-bit characters are used (UCSZ=7) the ninth bit must be read from the RXB8 bit inUCSR

125ATtiny23132543A–AVR–08/03extended I/O. Typically “LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and“CBR”.The receive function example reads a

126ATtiny23132543A–AVR–08/03Parity Checker The Parity Checker is active when the high USART Parity mode (UPM1) bit is set. Typeof Parity Check to be p

127ATtiny23132543A–AVR–08/03Asynchronous Clock RecoveryThe clock recovery logic synchronizes internal clock to the incoming serial frames. Fig-ure 56

128ATtiny23132543A–AVR–08/03Figure 58 shows the sampling of the stop bit and the earliest possible beginning of thestart bit of the next frame.Figure

129ATtiny23132543A–AVR–08/03The recommendations of the maximum receiver baud rate error was made under theassumption that the Receiver and Transmitter

13ATtiny23132543A–AVR–08/03AVR ATtiny2313 MemoriesThis section describes the different memories in the ATtiny2313. The AVR architecturehas two main me

130ATtiny23132543A–AVR–08/03Multi-processor Communication ModeSetting the Multi-processor Communication mode (MPCM) bit in UCSRA enables a fil-tering

131ATtiny23132543A–AVR–08/03USART Register DescriptionUSART I/O Data Register – UDRThe USART Transmit Data Buffer Register and USART Receive Data Buff

132ATtiny23132543A–AVR–08/03• Bit 5 – UDRE: USART Data Register EmptyThe UDRE flag indicates if the transmit buffer (UDR) is ready to receive new data

133ATtiny23132543A–AVR–08/03USART Control and Status Register B – UCSRB• Bit 7 – RXCIE: RX Complete Interrupt EnableWriting this bit to one enables in

134ATtiny23132543A–AVR–08/03USART Control and Status Register C – UCSRC• Bit 6 – UMSEL: USART Mode SelectThis bit selects between asynchronous and syn

135ATtiny23132543A–AVR–08/03• Bit 2:1 – UCSZ1:0: Character SizeThe UCSZ1:0 bits combined with the UCSZ2 bit in UCSRB sets the number of data bits(Char

136ATtiny23132543A–AVR–08/03Examples of Baud Rate SettingFor standard crystal and resonator frequencies, the most commonly used baud rates forasynchro

137ATtiny23132543A–AVR–08/03Table 58. Examples of UBRR Settings for Commonly Used Oscillator Frequencies (Continued)Baud Rate (bps)fosc = 3.6864 MHz

138ATtiny23132543A–AVR–08/03Table 59. Examples of UBRR Settings for Commonly Used Oscillator Frequencies (Continued)Baud Rate (bps)fosc = 8.0000 MHz

139ATtiny23132543A–AVR–08/03Table 60. Examples of UBRR Settings for Commonly Used Oscillator Frequencies(Continued)Baud Rate (bps)fosc = 16.0000 MHzU

14ATtiny23132543A–AVR–08/03Register File, the next 64 location the standard I/O memory, and the next 128 locationsaddress the internal data SRAM.The f

140ATtiny23132543A–AVR–08/03Universal Serial Interface – USIThe Universal Serial Interface, or USI, provides the basic hardware resources neededfor se

141ATtiny23132543A–AVR–08/03The Two-wire clock control unit can generate an interrupt when a start condition isdetected on the Two-wire bus. It can al

142ATtiny23132543A–AVR–08/03The Three-wire mode timing is shown in Figure 61. At the top of the figure is a USCKcycle reference. One bit is shifted in

143ATtiny23132543A–AVR–08/03The following code demonstrates how to use the USI module as a SPI Master with max-imum speed (fsck = fck/2):SPITransfer_F

144ATtiny23132543A–AVR–08/03Note that the first two instructions is for initialization only and needs only to be executedonce.These instructions sets

145ATtiny23132543A–AVR–08/03Figure 63. Two-wire Mode, Typical Timing DiagramReferring to the timing diagram (Figure 63.), a bus transfer involves the

146ATtiny23132543A–AVR–08/03Start Condition Detector The start condition detector is shown in Figure 64. The SDA line is delayed (in the rangeof 50 to

147ATtiny23132543A–AVR–08/03Note that the corresponding Data Direction Register to the pin must be set to one forenabling data output from the Shift R

148ATtiny23132543A–AVR–08/03Note that even when no wire mode is selected (USIWM1..0 = 0) the external clock input(USCK/SCL) are can still be used by t

149ATtiny23132543A–AVR–08/03Note: 1. The DI and USCK pins are renamed to Serial Data (SDA) and Serial Clock (SCL)respectively to avoid confusion betwe

15ATtiny23132543A–AVR–08/03Data Memory Access Times This section describes the general access timing concepts for internal memory access.The internal

150ATtiny23132543A–AVR–08/03• Bit 3..2 – USICS1..0: Clock Source SelectThese bits set the clock source for the Shift Register and counter. The data ou

151ATtiny23132543A–AVR–08/03Analog Comparator The Analog Comparator compares the input values on the positive pin AIN0 and nega-tive pin AIN1. When th

152ATtiny23132543A–AVR–08/03ing the corresponding interrupt handling vector. Alternatively, ACI is cleared by writing alogic one to the flag.• Bit 3 –

153ATtiny23132543A–AVR–08/03debugWIRE On-chip Debug SystemFeatures • Complete Program Flow Control• Emulates All On-chip Functions, Both Digital and A

154ATtiny23132543A–AVR–08/03• Capacitors inserted on the RESET pin must be disconnected when using debugWire.• All external reset sources must be disc

155ATtiny23132543A–AVR–08/03Self-Programming the FlashThe device provides a Self-Programming mechanism for downloading and uploadingprogram code by th

156ATtiny23132543A–AVR–08/03Addressing the Flash During Self-ProgrammingThe Z-pointer is used to address the SPM commands.Since the Flash is organized

157ATtiny23132543A–AVR–08/03Store Program Memory Control and Status Register – SPMCSRThe Store Program Memory Control and Status Register contains the

158ATtiny23132543A–AVR–08/03EEPROM Write Prevents Writing to SPMCSRNote that an EEPROM write operation will block all software programming to Flash.Re

159ATtiny23132543A–AVR–08/03Preventing Flash Corruption During periods of low VCC, the Flash program can be corrupted because the supply volt-age is t

16ATtiny23132543A–AVR–08/03The EEPROM Address Register• Bit 7 – Res: Reserved BitThis bit is reserved in the ATtiny2313 and will always read as zero.•

160ATtiny23132543A–AVR–08/03Memory ProgrammingProgram And Data Memory Lock BitsThe ATtiny2313 provides two Lock bits which can be left unprogrammed (“

161ATtiny23132543A–AVR–08/03Fuse Bits The ATtiny2313 has three Fuse bytes. Table 68 and Table 69 describe briefly the func-tionality of all the fuses

162ATtiny23132543A–AVR–08/03Note: 1. The default value of SUT1..0 results in maximum start-up time for the default clocksource. See Table 15 on page 3

163ATtiny23132543A–AVR–08/03Parallel Programming Parameters, Pin Mapping, and CommandsThis section describes how to parallel program and verify Flash

164ATtiny23132543A–AVR–08/03Table 71. Pin Values Used to Enter Programming ModePin Symbol ValueXA1 Prog_enable[3] 0XA0 Prog_enable[2] 0BS1 Prog_enabl

165ATtiny23132543A–AVR–08/03Serial Programming Pin MappingParallel ProgrammingEnter Programming Mode The following algorithm puts the device in parall

166ATtiny23132543A–AVR–08/03Programming the Flash The Flash is organized in pages, see Table 74 on page 164. When programming theFlash, the program da

167ATtiny23132543A–AVR–08/03I. Repeat B through H until the entire Flash is programmed or until all data has beenprogrammed.J. End Page Programming1.

168ATtiny23132543A–AVR–08/03Programming the EEPROM The EEPROM is organized in pages, see Table 75 on page 164. When programmingthe EEPROM, the program

169ATtiny23132543A–AVR–08/03Reading the EEPROM The algorithm for reading the EEPROM memory is as follows (refer to “Programming theFlash” on page 166

17ATtiny23132543A–AVR–08/03• Bit 3 – EERIE: EEPROM Ready Interrupt EnableWriting EERIE to one enables the EEPROM Ready Interrupt if the I-bit in SREG

170ATtiny23132543A–AVR–08/03Programming the Lock Bits The algorithm for programming the Lock bits is as follows (refer to “Programming theFlash” on pa

171ATtiny23132543A–AVR–08/03Reading the Calibration Byte The algorithm for reading the Calibration byte is as follows (refer to “Programming theFlash”

172ATtiny23132543A–AVR–08/03Figure 76. Parallel Programming Timing, Reading Sequence (within the Same Page)with Timing Requirements(1)Note: 1. The ti

173ATtiny23132543A–AVR–08/03Notes: 1. tWLRH is valid for the Write Flash, Write EEPROM, Write Fuse bits and Write Lockbits commands.2. tWLRH_CE is v

174ATtiny23132543A–AVR–08/03Serial Programming AlgorithmWhen writing serial data to the ATtiny2313, data is clocked on the rising edge of SCK.When rea

175ATtiny23132543A–AVR–08/03Data Polling EEPROM When a new byte has been written and is being programmed into EEPROM, reading theaddress location bein

176ATtiny23132543A–AVR–08/03Note: a = address high bits, b = address low bits, H = 0 - Low byte, 1 - High Byte, o = data out, i = data in, x = don’t c

177ATtiny23132543A–AVR–08/03Note: 1. 2 tCLCL for fck < 12 MHz, 3 tCLCL for fck >= 12 MHzTable 80. Serial Programming Characteristics, TA = -40°

178ATtiny23132543A–AVR–08/03Electrical CharacteristicsAbsolute Maximum Ratings*Notes: 1. All DC Characteristics contained in this data sheet are based

179ATtiny23132543A–AVR–08/034. Although each I/O port can sink more than the test conditions (10 mA at VCC = 5V, 5 mA at VCC = 3V) under steady statec

18ATtiny23132543A–AVR–08/03Erase To erase a byte, the address must be written to EEAR. If the EEPMn bits are 0b01, writ-ing the EEPE (within four cycl

180ATtiny23132543A–AVR–08/03External Clock Drive WaveformsFigure 80. External Clock Drive WaveformsExternal Clock DriveFigure 81. Maximum Frequency

181ATtiny23132543A–AVR–08/03ATtiny2313 Typical Characteristics – Preliminary DataThe following charts show typical behavior. These figures are not tes

182ATtiny23132543A–AVR–08/03Figure 83. Active Supply Current vs. Frequency (1 - 16 MHz)Figure 84. Active Supply Current vs. VCC (Internal RC Oscilla

183ATtiny23132543A–AVR–08/03Figure 85. Active Supply Current vs. VCC (Internal RC Oscillator, CKDIV8Programmed, 1.0 MHz)Idle Supply Current Figure 86

184ATtiny23132543A–AVR–08/03Figure 87. Idle Supply Current vs. Frequency (1 - 16 MHz)Figure 88. Idle Supply Current vs. VCC (Internal RC Oscillator,

185ATtiny23132543A–AVR–08/03Figure 89. Idle Supply Current vs. VCC (Internal RC Oscillator, CKDIV8 Programmed,1.0 MHz)Power-down Supply Current Figur

186ATtiny23132543A–AVR–08/03Figure 91. Power-down Supply Current vs. VCC (Watchdog Timer Enabled)Pin Pull-up Figure 92. I/O Pin Pull-up Resistor Cur

187ATtiny23132543A–AVR–08/03Figure 93. I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 2.7V)Figure 94. I/O Pin Pull-up Resistor Current vs

188ATtiny23132543A–AVR–08/03Figure 95. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 5V)Figure 96. Reset Pull-up Resistor Current vs.

189ATtiny23132543A–AVR–08/03Figure 97. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 1.8V)Pin Thresholds and hysteresisFigure 98. I/O

19ATtiny23132543A–AVR–08/03The following code examples show one assembly and one C function for writing to theEEPROM. The examples assume that interru

190ATtiny23132543A–AVR–08/03Figure 99. I/O Pin Input Threshold Voltage vs. VCC (VIL, I/O Pin Read as “0”)Figure 100. I/O Pin Input Hysteresis vs. VC

191ATtiny23132543A–AVR–08/03Figure 101. Reset Input Threshold Voltage vs. VCC (VIH,Reset Pin Read as “1”)Figure 102. Reset Input Threshold Voltage v

192ATtiny23132543A–AVR–08/03BOD Thresholds and Analog Comparator OffsetFigure 103. BOD Thresholds vs. Temperature (BOD Level is 4.3V)Figure 104. BOD

193ATtiny23132543A–AVR–08/03Figure 105. BOD Thresholds vs. Temperature (BOD Level is 1.8V)Figure 106. Bandgap Voltage vs. VCC BOD THRESHOLDS vs. TEM

194ATtiny23132543A–AVR–08/03Figure 107. Analog Comparator Offset Voltage vs. Common Mode Voltage (VCC = 5V)Figure 108. Analog Comparator Offset Volt

195ATtiny23132543A–AVR–08/03Current Consumption of Peripheral UnitsFigure 109. Brownout Detector Current vs. VCC Figure 110. Analog Comparator Curre

196ATtiny23132543A–AVR–08/03Figure 111. Programming Current vs. VCC Current Consumption in Reset and Reset PulsewidthFigure 112. Reset Supply Curren

197ATtiny23132543A–AVR–08/03Figure 113. Reset Supply Current vs. VCC (1 - 20 MHz, Excluding Current Through TheReset Pull-up)Figure 114. Minumum Res

198ATtiny23132543A–AVR–08/03Register SummaryAddress Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page0x3F (0x5F) SREG I T H S V N Z C 70x3E (0

199ATtiny23132543A–AVR–08/03Note: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory a

2ATtiny23132543A–AVR–08/03Overview The ATtiny2313 is a low-power CMOS 8-bit microcontroller based on the AVRenhanced RISC architecture. By executing p

20ATtiny23132543A–AVR–08/03The next code examples show assembly and C functions for reading the EEPROM. Theexamples assume that interrupts are control

200ATtiny23132543A–AVR–08/03Instruction Set SummaryMnemonics Operands Description Operation Flags #ClocksARITHMETIC AND LOGIC INSTRUCTIONSADD Rd, Rr A

201ATtiny23132543A–AVR–08/03ROR Rd Rotate Right Through Carry Rd(7)←C,Rd(n)← Rd(n+1),C←Rd(0) Z,C,N,V 1ASR Rd Arithmetic Shift Right Rd(n) ← Rd(n+1), n

202ATtiny23132543A–AVR–08/03Ordering Information(1)Note: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales offi

203ATtiny23132543A–AVR–08/03Packaging Information20P3 2325 Orchard Parkway San Jose, CA 95131TITLEDRAWING NO.RREV. 20P3, 20-lead (0.300"/7.62

204ATtiny23132543A–AVR–08/0320S2325 Orchard ParkwaySan Jose, CA 95131TITLEDRAWING NO.RREV. 20S2, 20-lead, 0.300" Wide Body, Plastic GullWing Sm

205ATtiny23132543A–AVR–08/0332M1-A 2325 Orchard Parkway San Jose, CA 95131TITLEDRAWING NO.RREV. 32M1-A, 32-pad, 5 x 5 x 1.0 mm Body, Lead Pitch 0.

206ATtiny23132543A–AVR–08/03

iATtiny23132543A–AVR–08/03Table of Contents Features...

iiATtiny23132543A–AVR–08/03Timed Sequences for Changing the Configuration of the Watchdog Timer ... 44Interrupts...

iiiATtiny23132543A–AVR–08/03USART Register Description ... 131Examples of Bau

21ATtiny23132543A–AVR–08/03I/O Memory The I/O space definition of the ATtiny2313 is shown in “Register Summary” on page198.All ATtiny2313 I/Os and per

ivATtiny23132543A–AVR–08/03Packaging Information... 20320P3 ...

Printed on recycled paper.Disclaimer: Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Co

22ATtiny23132543A–AVR–08/03System Clock and Clock OptionsClock Systems and their DistributionFigure 11 presents the principal clock systems in the AVR

23ATtiny23132543A–AVR–08/03Clock Sources The device has the following clock source options, selectable by Flash Fuse bits asshown below. The clock fro

24ATtiny23132543A–AVR–08/03Crystal Oscillator XTAL1 and XTAL2 are input and output, respectively, of an inverting amplifier which canbe configured for

25ATtiny23132543A–AVR–08/03Notes: 1. These options should only be used when not operating close to the maximum fre-quency of the device, and only if f

26ATtiny23132543A–AVR–08/03When this Oscillator is selected, start-up times are determined by the SUT Fuses asshown in Table 7.Note: 1. The device is

27ATtiny23132543A–AVR–08/03External Clock To drive the device from an external clock source, XTAL1 should be driven as shown inFigure 13. To run the d

28ATtiny23132543A–AVR–08/03128 kHz Internal OscillatorThe 128 kHz Internal Oscillator is a low power Oscillator providing a clock of 128 kHz.The frequ

29ATtiny23132543A–AVR–08/03frequency than the maximum frequency of the device at the present operating condi-tions. The device is shipped with the CKD

3ATtiny23132543A–AVR–08/03The AVR core combines a rich instruction set with 32 general purpose working registers.All the 32 registers are directly con

30ATtiny23132543A–AVR–08/03Power Management and Sleep ModesSleep modes enable the application to shut down unused modules in the MCU, therebysaving po

31ATtiny23132543A–AVR–08/03Idle Mode When the SM1..0 bits are written to 00, the SLEEP instruction makes the MCU enterIdle mode, stopping the CPU but

32ATtiny23132543A–AVR–08/03Minimizing Power ConsumptionThere are several issues to consider when trying to minimize the power consumption inan AVR con

33ATtiny23132543A–AVR–08/03Port Pins When entering a sleep mode, all port pins should be configured to use minimum power.The most important is then to

34ATtiny23132543A–AVR–08/03System Control and ResetResetting the AVR During reset, all I/O Registers are set to their initial values, and the program

35ATtiny23132543A–AVR–08/03Notes: 1. Values are guidelines only. Actual values are TBD.2. The Power-on Reset will not work unless the supply voltage h

36ATtiny23132543A–AVR–08/03Figure 16. MCU Start-up, RESET Extended ExternallyExternal Reset An External Reset is generated by a low level on the RESE

37ATtiny23132543A–AVR–08/03Note: 1. VBOT may be below nominal minimum operating voltage for some devices. Fordevices where this is the case, the devic

38ATtiny23132543A–AVR–08/03Watchdog Reset When the Watchdog times out, it will generate a short reset pulse of one CK cycle dura-tion. On the falling

39ATtiny23132543A–AVR–08/03Internal Voltage ReferenceATtiny2313 features an internal bandgap reference. This reference is used for Brown-out Detection

4ATtiny23132543A–AVR–08/03Pin DescriptionsVCC Digital supply voltage.GND Ground.Port A (PA2..PA0) Port A is a 3-bit bi-directional I/O port with inter

40ATtiny23132543A–AVR–08/03Watchdog Timer The Watchdog Timer is clocked from an On-chip Oscillator which runs at 128 kHz. Bycontrolling the Watchdog T

41ATtiny23132543A–AVR–08/03• Bit 6 – WDIE: Watchdog Timeout Interrupt EnableWhen this bit is written to one, WDE is cleared, and the I-bit in the Stat

42ATtiny23132543A–AVR–08/03• Bits 5, 2..0 – WDP3..0: Watchdog Timer Prescaler 3, 2, 1, and 0The WDP3..0 bits determine the Watchdog Timer prescaling w

43ATtiny23132543A–AVR–08/03The following code example shows one assembly and one C function for turning off theWDT. The example assumes that interrupt

44ATtiny23132543A–AVR–08/03Timed Sequences for Changing the Configuration of the Watchdog TimerThe sequence for changing configuration differs slightl

45ATtiny23132543A–AVR–08/03Interrupts This section describes the specifics of the interrupt handling as performed inATtiny2313. For a general explanat

46ATtiny23132543A–AVR–08/03The most typical and general program setup for the Reset and Interrupt VectorAddresses in ATtiny2313 is:Address Labels Code

47ATtiny23132543A–AVR–08/03I/O-PortsIntroduction All AVR ports have true Read-Modify-Write functionality when used as general digitalI/O ports. This m

48ATtiny23132543A–AVR–08/03Note that enabling the alternate function of some of the port pins does not affect the useof the other pins in the port as

49ATtiny23132543A–AVR–08/03Toggling the Pin Writing a logic one to PINxn toggles the value of PORTxn, independent on the value ofDDRxn. Note that the

5ATtiny23132543A–AVR–08/03AVR CPU CoreIntroduction This section discusses the AVR core architecture in general. The main function of theCPU core is to

50ATtiny23132543A–AVR–08/03Consider the clock period starting shortly after the first falling edge of the system clock.The latch is closed when the cl

51ATtiny23132543A–AVR–08/03The following code example shows how to set port B pins 0 and 1 high, 2 and 3 low, anddefine the port pins from 4 to 7 as i

52ATtiny23132543A–AVR–08/03Alternate Port Functions Most port pins have alternate functions in addition to being general digital I/Os. Figure25 shows

53ATtiny23132543A–AVR–08/03The following subsections shortly describe the alternate functions for each port, andrelate the overriding signals to the a

54ATtiny23132543A–AVR–08/03MCU Control Register – MCUCR• Bit 7 – PUD: Pull-up DisableWhen this bit is written to one, the pull-ups in the I/O ports ar

55ATtiny23132543A–AVR–08/03PCINT6: Pin Change Interrupt Source 6. The PB6 pin can serve as an external interruptsource.• DI/SDA/PCINT5 - Port B, Bit 5

56ATtiny23132543A–AVR–08/03• AIN1/PCINT1 – Port B, Bit 1AIN1: Analog Comparator Negative input and ADC6: ADC input channel 6. Configurethe port pin as

57ATtiny23132543A–AVR–08/03 Alternate Functions of Port D The Port D pins with alternate functions are shown in Table 29.The alternate pin configurati

58ATtiny23132543A–AVR–08/03• T0 – Port D, Bit 4CKOUT: System Clock OutputT0: Timer/Counter0 External Counter Clock input is enabled by setting (one) t

59ATtiny23132543A–AVR–08/03 Table 31. Overriding Signals for Alternate Functions in PD3..PD0Signal Name PD3/INT1PD2/INT0/XCK/CKOUT PD1/TXD PD0/RXDPUO

6ATtiny23132543A–AVR–08/03the operation is executed, and the result is stored back in the Register File – in oneclock cycle.Six of the 32 registers ca

60ATtiny23132543A–AVR–08/03Register Description for I/O-PortsPort A Data Register – PORTAPort A Data Direction Register – DDRAPort A Input Pins Addres

61ATtiny23132543A–AVR–08/03External Interrupts The External Interrupts are triggered by the INT0 pin, INT1 pin or any of the PCINT15..0pins. Observe t

62ATtiny23132543A–AVR–08/03• Bit 1, 0 – ISC01, ISC00: Interrupt Sense Control 0 Bit 1 and Bit 0The External Interrupt 0 is activated by the external p

63ATtiny23132543A–AVR–08/03External Interrupt Flag Register – EIFR• Bit 7 – INTF1: External Interrupt Flag 1When an edge or logic change on the INT1 p

64ATtiny23132543A–AVR–08/038-bit Timer/Counter0 with PWMTimer/Counter0 is a general purpose 8-bit Timer/Counter module, with two independentOutput Com

65ATtiny23132543A–AVR–08/03Compare pins (OC0A and OC0B). See “Output Compare Unit” on page 66. for details.The Compare Match event will also set the C

66ATtiny23132543A–AVR–08/03Depending of the mode of operation used, the counter is cleared, incremented, or dec-remented at each timer clock (clkT0).

67ATtiny23132543A–AVR–08/03The OCR0x Registers are double buffered when using any of the Pulse Width Modula-tion (PWM) modes. For the normal and Clear

68ATtiny23132543A–AVR–08/03Compare Match Output UnitThe Compare Output mode (COM0x1:0) bits have two functions. The Waveform Gener-ator uses the COM0x

69ATtiny23132543A–AVR–08/03Modes of Operation The mode of operation, i.e., the behavior of the Timer/Counter and the Output Comparepins, is defined by

7ATtiny23132543A–AVR–08/03Status Register The Status Register contains information about the result of the most recently executedarithmetic instructio

70ATtiny23132543A–AVR–08/03to OCR0A is lower than the current value of TCNT0, the counter will miss the CompareMatch. The counter will then have to co

71ATtiny23132543A–AVR–08/03Figure 31. Fast PWM Mode, Timing DiagramThe Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches TOP. I

72ATtiny23132543A–AVR–08/03Phase Correct PWM Mode The phase correct PWM mode (WGM02:0 = 1 or 5) provides a high resolution phasecorrect PWM waveform g

73ATtiny23132543A–AVR–08/03and TCNT0 when the counter decrements. The PWM frequency for the output whenusing phase correct PWM can be calculated by th

74ATtiny23132543A–AVR–08/03Figure 34. Timer/Counter Timing Diagram, with Prescaler (fclk_I/O/8)Figure 35 shows the setting of OCF0B in all modes and

75ATtiny23132543A–AVR–08/038-bit Timer/Counter Register DescriptionTimer/Counter Control Register A – TCCR0A• Bits 7:6 – COM0A1:0: Compare Match Outpu

76ATtiny23132543A–AVR–08/03Table 37 shows the COM0A1:0 bit functionality when the WGM02:0 bits are set tophase correct PWM mode.Note: 1. A special cas

77ATtiny23132543A–AVR–08/03Table 40 shows the COM0B1:0 bit functionality when the WGM02:0 bits are set tophase correct PWM mode.Note: 1. A special cas

78ATtiny23132543A–AVR–08/03Timer/Counter Control Register B – TCCR0B• Bit 7 – FOC0A: Force Output Compare AThe FOC0A bit is only active when the WGM b

79ATtiny23132543A–AVR–08/03If external pin modes are used for the Timer/Counter0, transitions on the T0 pin willclock the counter even if the pin is c

8ATtiny23132543A–AVR–08/03• Bit 0 – C: Carry FlagThe Carry Flag C indicates a carry in an arithmetic or logic operation. See the “Instruc-tion Set Des

80ATtiny23132543A–AVR–08/03• Bit 1 – TOIE0: Timer/Counter0 Overflow Interrupt EnableWhen the TOIE0 bit is written to one, and the I-bit in the Status

81ATtiny23132543A–AVR–08/03Timer/Counter0 and Timer/Counter1 PrescalersTimer/Counter1 and Timer/Counter0 share the same prescaler module, but theTimer

82ATtiny23132543A–AVR–08/03the edge detector uses sampling, the maximum frequency of an external clock it candetect is half the sampling frequency (Ny

83ATtiny23132543A–AVR–08/0316-bit Timer/Counter1 The 16-bit Timer/Counter unit allows accurate program execution timing (event man-agement), wave gene

84ATtiny23132543A–AVR–08/03Figure 39. 16-bit Timer/Counter Block Diagram(1)Note: 1. Refer to Figure 1 on page 1 for Timer/Counter1 pin placement and

85ATtiny23132543A–AVR–08/03The Input Capture Register can capture the Timer/Counter value at a given external(edge triggered) event on either the Inpu

86ATtiny23132543A–AVR–08/03Accessing 16-bit RegistersThe TCNT1, OCR1A/B, and ICR1 are 16-bit registers that can be accessed by the AVRCPU via the 8-bi

87ATtiny23132543A–AVR–08/03Therefore, when both the main code and the interrupt code update the temporary regis-ter, the main code must disable the in

88ATtiny23132543A–AVR–08/03The following code examples show how to do an atomic write of the TCNT1 Registercontents. Writing any of the OCR1A/B or ICR

89ATtiny23132543A–AVR–08/03Timer/Counter Clock SourcesThe Timer/Counter can be clocked by an internal or an external clock source. The clocksource is

9ATtiny23132543A–AVR–08/03The X-register, Y-register, and Z-registerThe registers R26..R31 have some added functions to their general purpose usage.Th

90ATtiny23132543A–AVR–08/03how waveforms are generated on the Output Compare outputs OC1x. For more detailsabout advanced counting sequences and wavef

91ATtiny23132543A–AVR–08/03The ICR1 Register can only be written when using a Waveform Generation mode thatutilizes the ICR1 Register for defining the

92ATtiny23132543A–AVR–08/03Output Compare Units The 16-bit comparator continuously compares TCNT1 with the Output Compare Regis-ter (OCR1x). If TCNT e

93ATtiny23132543A–AVR–08/03(Buffer or Compare) Register is only changed by a write operation (the Timer/Counterdoes not update this register automatic

94ATtiny23132543A–AVR–08/03Compare Match Output UnitThe Compare Output mode (COM1x1:0) bits have two functions. The Waveform Gener-ator uses the COM1x

95ATtiny23132543A–AVR–08/03Compare Output Mode and Waveform GenerationThe Waveform Generator uses the COM1x1:0 bits differently in normal, CTC, and PW

96ATtiny23132543A–AVR–08/03Clear Timer on Compare Match (CTC) ModeIn Clear Timer on Compare or CTC mode (WGM13:0 = 4 or 12), the OCR1A or ICR1Register

97ATtiny23132543A–AVR–08/03Fast PWM Mode The fast Pulse Width Modulation or fast PWM mode (WGM13:0 = 5, 6, 7, 14, or 15) pro-vides a high frequency PW

98ATtiny23132543A–AVR–08/03When changing the TOP value the program must ensure that the new TOP value ishigher or equal to the value of all of the Com

99ATtiny23132543A–AVR–08/03Phase Correct PWM Mode The phase correct Pulse Width Modulation or phase correct PWM mode (WGM13:0 = 1,2, 3, 10, or 11) pro