
4
6577CS–SMS–06/10
AT90SC28880RCFV
Figure 1. The AT90SC28880RCFV secureAVR Enhanced RISC Architecture
Instruction
Decoder
Program
Memory
Instruction
Register
Access
Control
General
Purpose
Registers
X
Y
Z
Status
Register
AdvX
Crypto-
Coprocessor
RAM
Data Memory
Interrupt
Unit
ISO 7816
I/O Port 0
Timer
Control
Lines
ALU
EEPROM
User Memory
OTP
PC
Secure
Control
V
CC
GND
CLK
Access
Control
IN/OUT0
Data Bus
8-bit
RNG
16
16
16
8
88
DES
DPA Counter
measures
Reset
Circuit
RST
ISO 7816
Controller
CRC and
Cheksum
CRYPTO
ROM
ISO 14443
Controller
DMA
RF
Front-End
RF1
RF2
AES
CSM
Secure
Control
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