Rainbow-electronics MAX3671 Manual do Utilizador descarregar pdf

General Description

The MAX3671 is a low-jitter frequency synthesizer that

accepts two reference clock inputs and generates nine

phase-aligned outputs. The device features 40kHz jitter

transfer bandwidth, 0.3ps

RMS

(12kHz to 20MHz) inte-

grated phase jitter, and best-in-class power-supply

noise rejection (PSNR), making it ideal for jitter clean-

up, frequency translation, and clock distribution in

Gigabit Ethernet applications.

The MAX3671 operates from a single +3.3V supply and

typically consumes 400mW. The IC is available in an

8mm x 8mm, 56-pin TQFN package, and operates from

-40°C to +85°C.

Applications

Gigabit Ethernet Routers and Switches

Frequency Translation

Jitter Cleanup

Clock Distribution

Features

♦ Two Reference Clock Inputs: LVPECL

♦ Nine Phase-Aligned Clock Outputs: LVPECL

♦ Input Frequencies: 62.5MHz,125MHz, 250MHz,

312.5MHz

♦ Output Frequencies: 62.5MHz, 125MHz,

156.25MHz, 250MHz, 312.5MHz

♦ Low-Jitter Generation: 0.3ps

RMS

(12kHz to 20MHz)

♦ Clock Failure Indicator for Both Reference Clocks

♦ External Feedback Provides Zero-Delay Capability

♦ Low Output Skew: 20ps Typical

MAX3671

Low-Jitter Frequency Synthesizer

with Selectable Input Reference

________________________________________________________________

Maxim Integrated Products

Ordering Information

19-4437; Rev 0; 2/09

For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,

or visit Maxim’s website at www.maxim-ic.com.

EVALUATION KIT

AVAILABLE

PART TEMP RANGE PIN-PACKAGE

MAX3671ETN+ -40°C to +85°C 56 TQFN-EP*

SIGNAL QUALIFIER

AND

LOCK DETECT

POWER-ON

RESET

(POR)

IN0FAIL

IN1FAIL

LOCK

REFCLK0

FB_INFB_SEL FB_IN

REFCLK1

DIV M

DMSEL_CLK

PFD CP

DIV N

DIV A

DIV B

VCO

2.5GHz62.5MHz

OUTA2

OUTA1

OUTA3

OUTA0

OUTB_EN

OUTA0

OUTA_ENPLL_BYPASS

OUTB3

OUTB2

OUTB4

OUTB1

OUTB0

PLL

0.1μF

REG

0.22μF

MAX3671

Functional Diagram

Denotes a lead(Pb)-free/RoHS-compliant package.

EP = Exposed pad.

Pin Configuration and Typical Application Circuits appear at

end of data sheet.

1 2 3 4 5 6 ... 15 16

Resumo do Conteúdo

Página 1 - Functional Diagram

General DescriptionThe MAX3671 is a low-jitter frequency synthesizer thataccepts two reference clock inputs and generates ninephase-aligned outputs. T

Página 2 - ELECTRICAL CHARACTERISTICS

MAX3671IN0FAIL and IN1FAIL, respectively. Once an indicatoris asserted low, it is latched and updated every 128PFD cycles (~ 2µs).It should be noted

Página 3

PLL Out-of-Lock ConditionIf the frequency difference between the reference clockinput and the VCO at the PFD input becomes within500ppm, the PLL is co

Página 4 - On-Reset (POR)

MAX3671Master ResetAfter power-up, an external master reset (MR) can beprovided to reset the internal dividers. This inputrequires a minimum reset pul

Página 5 - OVERSHOOT

Power Supply and Ground ConnectionsThe MAX3671 has seven supply connection pins;installation of a bypass capacitor at each supply pin isrecommended. A

Página 6 - = 3.3V, T

MAX3671Low-Jitter Frequency Synthesizer with Selectable Input Reference14 ____________________________________________________________________________

Página 7