
MAX9257/MAX9258
______________________________________________________________________________________ 41
Fully Programmable Serializer/Deserializer
with UART/I
2
C Control Channel
ADDRESS BITS DEFAULT NAME DESCRIPTION
Control channel end timeout: (ETO) times out if ECU does not use control channel for this amount of time after it has
already used at least once.
7:4 1010 ETODIV
Control channel end timeout divider
Pixel clock is first divided by:
0000 = 16 1000 = 256
0001 = 16 1001 = 512
0010 = 16 1010 = 1024 (default)
0011 = 16 1011 = 2048
0100 = 16 1100 = 4096
0101 = 32 1101 = 8192
0110 = 64 1110 = 16,384
0111 = 128 1111 = 32,768
3
3:0 0000 ETOCNT
Control channel end timeout counter
Divided pixel clock is used to count up to (ETOCNT + 1)
7 0 VEDGE
VSYNC active edge at camera interface
0 = falling (default), 1 = rising
6 0 Reserved (set to 0)
5 1 CKEDGE
PCLK active edge at camera interface
0 = falling, 1 = rising (default)
40 PD
Power mode
0 = power-up, 1 = power-down
(when REM = 1 default is 1)
3 1 SEREN
Serialization enable
0 = disabled, 1 = enabled
(when REM = 1 default is 0)
2 0 BYPFPLL
Bypass filter PLL
0 = active (default), 1 = bypass
1 0 Reserved (set to 0)
4
0 0 PRBSEN
PRBS test enable
0 = disabled (default), 1 = enabled
7:1 1111101 DEVICEID 7-bit address of MAX9257
5
0 0 Reserved (set to 0)
7:1 1111111 EF End frame to close control channel
6
0 1 Reserved (set to 1)
7:1 1111100 DESID 7-bit address ID of MAX9258
7
0 0 Reserved (set to 0)
MAX9257 Register Table (continued)
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